Philips Semiconductors

Product specification

SC28C94

Quad universal asynchronous receiver/transmitter (QUART)

1998 Aug 19

26

NO

FIGURE

CHARACTERISTIC

LIMITS

UNIT

NO.

FIGURE

CHARACTERISTIC

Min

Typ

Max

UNIT

1

6

Setup: A[5:0] valid to CEN Low

10

ns

2

6

45

ns

3

6

Access: Later of CEN Low and RDN Low, to Dnn valid (read)

110/115

ns

4

6

Later of CEN Low and (RDN or WRN as applicable) Low, to DACKN Low

ns

Normal Operation:

10 + 2

90/122 + 3

From Power Down:

150

5

6

0

30

ns

6

6

Earlier of CEN High or (RDN or WRN as applicable) High, to DACKN released

0

30

ns

7

6

Earlier of CEN High or (RDN or WRN as applicable) High, in one cycle, to later

of CEN Low and (RDN or WRN as applicable) Low, for the next cycle

50

ns

8

6

–30

ns

9

6

Later of CEN Low and WRN Low, to earlier of CEN High or WRN High

110/115

ns

10

6

0

ns

NOTES:

1. The minimum time indicates that read data will remain valid until the bus master drives CEN and/or RDN to High.

2. The fact that this parameter is negative means that the Dnn line may actually become valid after CEN and WRN are both Low.

3. In a Write operation, the bus master must hold the write data valid either until drives CEN and/or WRN to High, or until the QUART drives

DACKN to Low, whichever comes first.

5. Consecutive write operations to the upper four bits of the Command Register (CR) require at least three X1/CLK edges; four X1/CLK edges

in the ‘X1/CLK divide by 2 edges’ according to register 2E or 2F setting.

6. Address is latched at leading edge of a read or write cycle.

A[5:0]

CEN

RDN

WRN

D[7:0]

12

1

2

READ CYCLE

WRITE CYCLE

DACKN

4

4

3

3

7

7

9

9

7

7

9

9

5

5

6

6

8

8

4

4

10

10

10

6

6

SD00677

X1/CLK

Figure 6. A Read Cycle Followed by a Write Cycle with DACKN