SC28C94 datasheet(19/38 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC28C94

Quad universal asynchronous receiver/transmitter (QUART)

1998 Aug 19

In the timer mode, this bit is set once each cycle of the generated

square wave (every other time the C/T reaches zero count). The bit

is reset by a stop counter command. The command, however, does

not stop the C/T.

ISR[2] – Channel a Change in Break

This bit, when set, indicates that the receiver has detected the

beginning or the end of a received break. It is reset when the CPU

issues a reset break change interrupt command.

ISR[1] – Receiver Ready or FIFO Full Channel a

See the description of ISR[5]. The channel ‘a’ receiver operation is

the same as channel ‘b’.

ISR[0] – Transmitter Ready Channel a

See the description of ISR[4]. Channel “a” transmitter operates in

the same manner as channel “b.”

IMR – Interrupt Mask Register

The programming of this register selects which interrupt sources will

be allowed to enter the interrupt arbitration process. This register is

logically ANDED with the interrupt status register. Its function is to

allow the interrupt source it represents to join the bidding process if

the corresponding IMR and ISR bits are both 1. It has no effect on

the value in the ISR. It does not mask the reading of the ISR.

CTUR and CTLR – Counter/Timer Registers

The CTUR and CTLR hold the eight MSBs and eight LSBs,

respectively, of the value to be used by the counter/timer in either

the counter or timer modes of operation. The minimum value which

may be loaded into the CTUR/CTLR registers is H‘0002’. Note that

these registers are write-only and cannot be read by the CPU.

In the timer (programmable divider) mode, the C/T generates a

square wave with a period of twice the value (in clock periods) of

the CTUR and CTLR. If the value in CTUR or CTLR is changed, the

current half-period will not be affected, but subsequent half-periods

will be. The C/T will not be running until it receives an initial ‘Start

Counter’ command (read address at A5–A0 0Eh for C/T ab or read

address 1Eh for C/T cd ). After this, while in timer mode, the C/T will

run continuously. Receipt of a subsequent start counter command

causes the C/T to terminate the current timing cycle and to begin a

new cycle using the values in the CTUR and CTLR.

The counter ready status bit (ISR[3]) is set once each cycle of the

square wave. The bit is reset by a “Stop Counter” command (read

address at A5–A0 0Fh for C/T ab or read address 1Fh for C/T cd).

The command, however, does not stop the C/T. It only resets the

ISR[3] bit; the C/T continues to run. The ISR[3] bit will set again as

the counter passes through 0. The generated square wave is output

on an I/O pin if it is programmed to be the C/T output.

In the counter mode, the C/T counts down the number of pulses

loaded in CTUR and CTLR by the CPU. Counting begins upon

receipt of a start counter command. Upon reaching the terminal

count H‘0000’, the counter ready interrupt bit (ISR[3]) is set. The

counter rolls over to 65535 and continues counting until stopped by

the CPU. If I/O is programmed to be the output of the C/T, the output

remains High until the terminal count is reached, at which time it

goes Low. The output returns to the High state and ISR[3] is cleared

when the counter is stopped by a stop counter command. The CPU

may change the values of CTUR and CTLR at any time, but the new

count becomes effective only on the next start counter command. If

new values have not been loaded, the previous values are

preserved and used for the next count cycle.

In the counter mode, the current value of the upper and lower eight

bits of the counter (CTU, CTL) may be read by the CPU. It is

recommended that the counter be stopped when reading to prevent

potential problems which may occur if a carry from the lower eight

bits to the upper eight bits occurs between the times that both

halves of the counter is read. However, note that a subsequent start

counter command will cause the counter to begin a new count cycle

using the values in CTUR and CTLR.

I/O LOGIC

The QUART has four I/O pins for each channel. These pins may be

individually programmed as an input or output under control of the

I/OPCR (I/O Port Control Register). Functions which may use the

I/O pins as inputs (Rx or Tx external clock, for example) are always

sensitive to the signal on the I/O pin regardless of it being

programmed as an input or an output. For example if I/O1a was

programmed to output the RxC1X clock and the Counter/Timer was

programmed to use I/O pin as its clock input the result would be the

Counter/Timer being clocked by the RxC1X clock.

The 16 I/O ports are accessed and/or controlled by five (5) registers:

IPR, ACR, I/OPCR, IPCR, OPR. They are shown in Table 8 of this

document. Each UART has four pins. Two of these pins have

“Change of State Detectors” (COS). These detectors set

whenever the pin to which they are attached changes state. (1 to 0

or 0 to 1) The “Change of State Detectors” are enabled via the

ACR. When enabled the COS devices may generate interrupts via

the IMR and IPCR registers. Note that when the COS interrupt is

enabled that any one or more of the four COS bits in the IPCR will

enable the COS bidding. Each of the channel’s four I/O lines are

configured as inputs on reset.

The Change of State detectors sample the I/O pins at the rate of the

38.4KHz clock. A change on the pin will be required to be stable for

at least 26.04

µs and as much as 52.08µs for the COS detectors to

confirm a change. Note that changes in the X1/clock frequency will

effect this stability requirement.

COS detectors are reset by a read of the IPCR.

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