SC28C94 datasheet(16/38 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC28C94

Quad universal asynchronous receiver/transmitter (QUART)

1998 Aug 19

time into the stop bit position). At this time the receiver has

finished processing the present character and is ready to

search for the start bit of the next character.

Table 5. Bit Rate Generator Characteristics

Crystal or Clock = 3.6864MHz

NORMAL RATE

(BAUD)

ACTUAL 16X

CLOCK (kHz)

ERROR (%)

110

134.5

150

200

300

600

1050

1200

1800

2000

2400

4800

7200

9600

19.2K

38.4K

0.8

1.2

1.759

2.153

2.4

3.2

4.8

9.6

16.756

19.2

28.8

32.056

38.4

76.8

115.2

153.6

307.2

614.4

-0.069

0.059

-0.260

0.175

NOTE: Duty cycle of 16X clock is 50%

± 1%.

CR – Command Register

CR is used to write commands to the QUART.

CR[7:4] – Miscellaneous Commands

Issuing commands contained in the upper four bits of the “Command

edges. Allow four (4) edges if the “X1 clock divide by 2” mode is

used. The encoded value of this field can be used to specify a single

command as follows:

0000

No command.

0001

Reset MR pointer. Causes the MR pointer to point to MR1.

0010

Reset receiver. Resets the receiver as if a hardware reset

had been applied. The receiver is disabled and the FIFO

pointer is reset to the first location.

0011

Reset transmitter. Resets the transmitter as if a hardware

reset had been applied.

0100

Reset error status. Clears the received break, parity error,

framing error, and overrun error bits in the status register

(SR[7:4]}. Used in character mode to clear OE status

(although RB, PE, and FE bits will also be cleared), and in

block mode to clear all error status after a block of data

has been received.

0101

Reset break change interrupt. Causes the break detect

change bit in the interrupt status register (ISR[2 or 6]) to

be cleared to zero.

0110

Start break. Forces the TxD output low (spacing). If the

transmitter is empty, the start of the break condition will be

delayed up to two bit times. If the transmitter is active, the

break begins when transmission of the character is

completed. If a character is in the TxFIFO, the start of break

is delayed until that character or any others loaded after it

have been transmitted (TxEMT must be true before break

begins). The transmitter must be enabled to start a break

0111

Stop break. The TxD line will go high (marking) within two

bit times. TxD will remain high for one bit time before the

next character, if any, is transmitted.

1000

Assert RTSN. Causes the RTSN output to be asserted

(Low).

1001

Negate RTSN. Causes the RTSN output to be negated

(High).

1010

Set Timeout Mode On. The register in this channel will

restart the C/T as each receive character is transferred

from the shift register to the RxFIFO. The C/T is placed in

the counter mode, the START/STOP counter commands

are disabled, the counter is stopped, and the Counter

Ready Bit, ISR[3], is reset.

Only one receiver should use this mode at a time.

However, if both are on, the timeout occurs after both

receivers have been inactive for the timeout. The start of

the C/T will be on the logical ‘OR’ of the two receivers.

See “Timeout Mode Caution” paragraph.

1011

Set MR Pointer to 0.

1100

Disable Timeout Mode. This command returns control of

the C/T to the regular START/STOP counter commands.

It does not stop the counter, or clear any pending

interrupts. After disabling the timeout mode, a ‘Stop

Counter’ command should be issued.

1101

Set Block Error Mode. Sets error bits in states register as

bytes are loaded to the FIFO. Normal byte error reporting

occurs when a byte is read from the FIFO on a per

character basis. This mode enables the error to be set as

the byte is loaded to the FIFO. This allows the control

software to “See” the error as soon as the byte is received.

Block error reporting (enabled by MR0 [5] = 1) accumulates

the error for the entire block of data. This will make it difficult

to locate the error on the particular byte(s) causing the error.

The block error mode of error accumulation is cleared

only by software reset of the individual receiver or by a

hardware reset of the entire chip.

111x

Reserved for testing.

CSR – Clock Select Register

CSR[7:4] – Receiver Clock Select

When using a 3.6864MHz crystal or external clock input, this field

selects the baud rate clock for the receiver as shown in Table 6.

The receiver clock is always a 16X clock, except for CSR[7:4] =

1111. I/O2x is external input.

CSR[3:0] – Transmitter Clock Select

This field selects the baud rate clock for the transmitter. The field

definition is as shown in Table 6, except as follows:

CSR[3:0]

ACR[7] = 0

ACR[7] = 1

1 1 1 0

I/O3x – 16X

1 1 1 1

I/O3x – 1X

CR[3] – Disable Transmitter

This command terminates transmitter operation and resets the

TxRDY and TxEMT status bits. However, if a character is being

transmitted or if a character is in the TxFIFO when the transmitter is

disabled, the transmission of the character(s) is completed before

assuming the inactive state.

While the transmitter is disabled (or a disable is pending), the

TxFIFO may not be loaded.

CR[2] – Enable Transmitter

Enables operation of the transmitter. The TxRDY and TxEMT status

bits will be asserted.

CR[1] – Disable Receiver

This command terminates operation of the receiver immediately – a

character being received will be lost. However any unread characters

in the RxFIFO area are still available. Disable is not the same as a

“receiver reset”. With a receiver reset any characters not read are

lost. The command has no effect on the receiver status bits or any

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