SC28C94 datasheet(22/38 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC28C94

Quad universal asynchronous receiver/transmitter (QUART)

1998 Aug 19

With Type = x11, the # Bytes field indicates the count of received

bytes available for reading, while with Type = x10 it indicates the

number of bytes that can be written to the transmit FIFO.

The CIR is Read only at address 28H.

Global Interrupt Byte Count (GIBC)

00000

# Bytes

The GIBC is not an actual register but simply outputs the interrupting

UART’s transmit or receive byte counter value. The count, accurate

at the time IACKN asserts, is captured in the CIR. The high order 5

bits are read as ‘0’. The GIBC is read only at address 2AH.

Global RxFIFO (GRxFIFO)

Received Data

If a receiver is not the cause of the current interrupt, a read of the

Global RxFIFO will yield a byte containing all ones and NONE of the

UART channels’ receive FIFOs will be popped. (IMPORTANT)

The GRxFIFO is Read only at address 2BH.

Global TxFIFO (GTxFIFO)

Data to be Sent

If a transmitter is not the cause of the current interrupt, a write to the

Global TxFIFO has no effect.

The GTxFIFO is Write only at address 2BH.

Global Interrupting Channel (GICR)

000000

Chan #

Like the other Global pseudo-registers no hardware register exists.

The Channel number field of the Current Interrupt Register padded

with leading zeros is output as the GICR. The GICR is Read only at

address 29H.

C/Tab indicated by Channel code B 01

C/Tcd indicated by Channel code D 11

Interrupt Control (ICR)

Threshold

IVC

The Threshold Field is used by the interrupt comparator to

determine if a winning interrupt “bid” should result in interrupting the

host MPU. The threshold field resets to 00.

The IVC field controls what kind of vector the QUART returns to the

host MPU during an Interrupt Acknowledge cycle:

Output contents of Interrupt Vector Register

Output 6 MSBs of IVR and Channel number as 2 LSBs

Output 3 MSBs of IVR, Interrupt Type and Channel number

Disable generation of vector during IACK cycle.

Returns hex’FF during an IACKN cycle.

The IVC field reset to 00. The ICR is read/write at address 2CH.

Bidding Control Registers (BCRs)

Received Break

State Change

C/T

This register is a transparent latch. It must be set to ensure the

expected operation of the arbitration system. The 3 MSBs

determine the priority of Received Break Interrupts; they are reset to

000.

Bits 4:2 determine the priority of Change of Input State interrupts,

and are reset to 00.

BCR Counter/Timer bits reset to 00.

There is one BCR per UART channel; they can be read or written at

addresses 20-23H.

Interrupt Vector (IVR)

The 8 bits of the interrupt vector

Interrupt Vector (IVR-Modified)

Always Used

with IVC = 0x

w/IVC = 01 or 10

Holds the constant bits of the interrupt acknowledge vector. As

shown, the three MSBs are always used, while the less significant

bits can be replaced by the interrupt type code and/or Channel code

bits contained in the CIR. The IVR is write only at address 29H.

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