SC28C94 datasheet(24/38 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC28C94

Quad universal asynchronous receiver/transmitter (QUART)

1998 Aug 19

AC ELECTRICAL CHARACTERISTICS1, 2, 3, 4

VCC = 5V ± 10%, TA = –40_C to 85_C, unless otherwise specified.

SYMBOL

FIGURE

PARAMETER

LIMITS

UNIT

SYMBOL

FIGURE

PARAMETER

Min

Typ

Max

UNIT

Reset timing

tRES

Reset pulse width

200

I/O Port timing

tPS

I/O input setup time before RDN Low

tPH

I/O input hold time after RDN High

tPD

I/O output valid from

WRN High (WRN or CEN high, whichever occurs first)

RDN Low (RDN or CEN low, whichever occurs last)

Interrupt timing

tIR

IRQN negated or I/O output High from:

Read RHR (RxRDY/FFULL interrupt)

Write THR (TxRDY interrupt)

Reset command (break change interrupt)

Reset command (I/O change interrupt)

Stop C/T command (counter interrupt)

Write IMR (clear of interrupt mask bit)

With respect to a

3.6864MHz clock

on pin X1/CLK

Clock timing

tCLK

X1/CLK low/high time

125/100

tCLK

X1/CLK low/high time (above 4MHz; X1/CLK

÷ 2 active)

56/56

tCLK5

X1/CLK frequency

3.6864

8.0

MHz

tCTC

Counter/timer clock high or low time

fCTC5

Counter/timer clock frequency

MHz

tRX

RxC high or low time

fRX5

RxC frequency (16X)

RxC frequency (1X)

1.0

MHz

tTX

TxC high or low time

fTX5

TxC frequency (16X)

TxC frequency (1X)

1.0

MHz

Transmitter timing

tTXD

TxD output delay from TxC low

tTCS

TxC output delay from TxD output data

–10

+10

Receiver timing

tRXS

RxD data setup time to RxC high

tRXH

RxD data hold time from RxC high

NOTES:

1. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 20ns

maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of VIL and VIH, as

appropriate.

2. Typical values are at +25oC, typical supply voltages, and typical processing parameters.

3. Test condition for interrupt and I/O outputs: CL = 50pF, RL = 2.7kΩ to VCC. Test conditions for rest of outputs: CL = 150pF.

4. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN

and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated

first terminates the cycle.

5. The minimum value is not tested, but is guaranteed by design. For tCLK minimum test rate is 2.0MHz.

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