Philips Semiconductors

Product specification

SC28C94

Quad universal asynchronous receiver/transmitter (QUART)

1998 Aug 19

25

NO

FIGURE

CHARACTERISTIC

LIMITS

UNIT

NO.

FIGURE

CHARACTERISTIC

Min

Typ

Max

UNIT

1

5

A[5:0] Setup time to RDN WRN Low

0

ns

2

5

A[5:0] Hold time from RDN WRN Low

45

ns

3

5

0

ns

4

5

0

ns

5

5

RDN WRN Pulse Width Low

65

ns

6

5

D[7:0] Data Valid after CEN and RDN Low

65

ns

7

5

D[7:0] Data Bus floating after RDN or CEN High

10

ns

8

5

D[7:0] Data Bus Setup time before WRN or CEN High

5

ns

9

5

D[7:0] Hold time after WRN or CEN High

0

ns

10

5

20

ns

NOTES:

1. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating

supply range.

2. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as a ‘strobing’ input. CEN and

RDN (also CEN and WRN) are ANDed internally. As a consequence the signal asserted last initiates the cycle; the signal negated first

terminates the cycle. Address is latched at leading edge of a read or write cycle.

3. The RDN signal must be negated for this time to guarantee that internal registers update before the next read.

A[5:0]

CEN

RDN

WRN

D[7:0]

12

1

2

10

5

7

READ CYCLE

WRITE CYCLE

3

5

6

4

8

9

SD00164

Figure 5. A Read Cycle Followed by a Write Cycle without DACKN