SC28C94 datasheet(17/38 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC28C94

Quad universal asynchronous receiver/transmitter (QUART)

1998 Aug 19

other control registers. If the special wake–up mode is programmed,

the receiver operates even if it is disabled (see Wake-up Mode).

CR[0] – Enable Receiver

Enables operation of the receiver. If not in the special wake-up

mode, this also forces the receiver into the search for start bit state.

Table 6.

Baud Rate

BRG RATE = LOW

BRG RATE = HIGH

TEST 1 = 1

CSR[7:4]

ACR[7] = 0

ACR[7] = 1

ACR[7] = 0

ACR[7] = 1

ACR[7] = 0

ACR[7] = 1

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

110

134.5

200

300

600

1,200

1,050

2,400

4,800

7,200

9,600

38.4k

Timer

I/O2 – 16X

I/O2 – 1X

110

38.4k

150

300

600

1,200

2,000

2,400

4,800

1,800

9,600

19.2k

Timer

I/O2 – 16X

I/O2 – 1X

300

110

134.5

1200

1800

3,600

7,200

1,050

14.4K

28.8K

7,200

57.6K

230.4K

Timer

I/O2 – 16X

I/O2 – 1X

450

110

134.5

900

1,800

3,600

7,200

2,000

14.4K

28.8K

1,800

57.6K

115.2K

Timer

I/O2 – 16X

I/O2 – 1X

4,800

880

1,076

19.2K

28.8K

57.6K

115.2K

1,050

57.6K

4,800

57.6K

9,600

38.4K

Timer

I/O2 – 16X

I/O2 – 1X

7,200

880

1,076

14.4K

28.8K

57.6K

115.2K

2,000

57.6K

4,800

14.4K

9,600

19.2K

Timer

I/O2 – 16X

I/O2 – 1X

SR – Channel Status Register

SR[7] – Received Break

This bit indicates that an all zero character of the programmed

length has been received without a stop bit. Only a single FIFO

position is occupied when a break is received; further entries to the

FIFO are inhibited until the RxDA line returns to the marking state

for at least one-half bit time two successive edges of the internal or

external 1X clock. This will usually require a high time of one X1

clock period or 3 X1 edges since the clock of the controller is

not synchronous to the X1 clock.

When this bit is set, the change in break bit in the ISR (ISR[6 or 2])

is set. ISR[6 or 2] is also set when the end of the break condition, as

defined above, is detected. The break detect circuitry is capable of

detecting breaks that originate in the middle of a received character.

However, if a break begins in the middle of a character, it must last

until the end of the next character in order for it to be detected.

SR[6] – Framing Error (FE)

This bit, when set, indicates that a stop bit was not detected when

the corresponding data character in the FIFO was received. The

stop bit check is made in the middle of the first stop bit position.

SR[5]– Parity Error (PE)

This bit is set when the ‘with parity’ or ‘force parity’ mode is

programmed and the corresponding character in the FIFO was

received with incorrect parity. In ‘wake-up mode’, the parity error bit

stores the received A/D (Address/Data) bit.

In the wake-up mode this bit follows the polarity of the A/D parity bit

as it is received. A parity of 1 would normally mean address and

therefore, the end of a data block.

SR[4] – Overrun Error (OE)

This bit, when set, indicates that one or more characters in the

received data stream have been lost. It is set upon receipt of a new

character when the FIFO is full and a character is already in the

receive shift register waiting for an empty FIFO position. When this

occurs, the character in the receive shift register (and its break

detect, parity error and framing error status, if any) is lost. This bit is

cleared by a reset error status command.

SRA[3] – Channel A Transmitter Empty (TxEMTA)

This bit will be set when the transmitter underruns, i.e., both the

TxEMT and TxRDY bits are set. This bit and TxRDY are set when

the transmitter is first enabled and at any time it is re-enabled after

either (a) reset, or (b) the transmitter has assumed the disabled

state. It is always set after transmission of the last stop bit of a

character if no character is in the THR awaiting transmission.

It is reset when the THR is loaded by the CPU, a pending

transmitter disable is executed, the transmitter is reset, or the

transmitter is disabled while in the underrun condition.

SR[2] – Transmitter Ready (TxRDY)

This bit, when set, indicates that the TxFIFO has at least one empty

location that may be loaded by the CPU. It sets when the transmitter

is first enabled. It is cleared when the TxFIFO is full (eight bytes);

the transmitter is reset; a pending transmitter disable is executed;

the transmitter is disabled when it is in the underrun condition. When

this bit is not set characters written to the TxFIFO will not be loaded

or transmitted; they are lost.

SR[1] – RxFIFO Full (FFULL)

This bit is set when a character is transferred from the receive shift

become full, i.e., all eight FIFO positions are occupied. It is reset

when the CPU reads the FIFO and there is no character in the

receive shift register. If a character is waiting in the receive shift

the FIFO once.

SR[0] – RxFIFO Ready (RxRDY)

This bit indicates that a character has been received and is waiting

in the FIFO to be read by the CPU. It is set when the character is

transferred from the receive shift register to the FIFO and reset

when the CPU reads the RxFIFO, and no more characters are in the

FIFO.

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