ADBMS2950BCCSZ datasheet(47/97 Pages) AD

47 / 97 page

Data Sheet

ADBMS2950B

Rev. 0 | Page 47 of 97

overcurrent detection is activated and changes to the respective

bit fields in the CFGB register do not affect the overcurrent

engine. New configurations in CFGB are activated only with the

next 0-to-1 transition on the OCEN bit.

When deactivating the overcurrent functionality through

changing OCEN from 1 to 0, the overcurrent engine does not

disable immediately. Instead, the deactivation only takes effect

once the ongoing OCxADC conversions finish and the

dependent registers (OCxR) and flags (OC1 to OC3L, OCAL,

and OCBL) are updated. This leads to a minimum wait time

requirement between the WRCFGA clearing the OCEN and

any subsequent command that reads (RDFLAG), freezes

(SNAP) or clears (CLRFLAG) the overcurrent alert flags or

reactivates the overcurrent engine (WRCFGA with OCEN = 1).

The required wait time between WRCFGA with OCEN = 0 and

WRCFGA with OCEN = 1 or CLRFLAG can be expressed as

follows:

tOCEN,DLY1 > max(tOCxADC) − t5 − (32 + N × 64) × tCLK

Where max(tOCxADC) is the maximum OCxADC conversion

time, t5 is the minimum CS idle time, N is the number of

devices written in the daisy-chain, and tCLK is the clock period of

the (iso)SPI interface. If positive, the host must wait this time. If

negative, no wait time is required as the length of the second

WRCFGA or the CLRFLAG command ensures already a

minimum time after OCEN clears.

The required wait time between WRCFGA with OCEN = 0 and

RDFLAG or SNAP can be expressed as follows:

tOCEN,DLY2 > max(tOCxADC) − t5 − 16 × tCLK

The wait time tOCEN,DLY2 is easily respected by proper command

sequencing that avoids RDFLAG or SNAP directly after the

WRCFGA.

The wait time tOCEN,DLY1 is typically required in the sequences for

the Overcurrent Configuration Update and the Crash Signal

Management.

Overcurrent Configuration Update

The overcurrent detection is activated while the OCEN bit is

set. To dynamically update the configuration from this state, at

least three write commands are required:

1. Send WRCFGB command with new configuration.

2. Send WRCFGA command with OCEN = 0.

3. Wait for tOCEN,DLY1 (no wait if tOCEN,DLY1 ≤ 0).

4. Send WRCFGA command with OCEN = 1.

Note:

•

While it is recommended to minimize the time in

which the overcurrent detection is inactive, the OCEN

must be disabled for at least one OCxADC conversion

time (tOCxADC), which is ensured by the wait time

tOCEN,DLY1.

•

It is recommended to set the bit OCDP in step 1 for

the reduced interval of 3 OCxADC conversion cycles

during which the OCx pins have high impedance.

•

The deglitchers are reset at step 4. In case an

overcurrent condition is present already before the

reconfiguration but not yet long enough to ignite the

pyrofuse, this leads to an increased latency equal to

one deglitching time window.

The successful update of the new settings can be verified by

issuing a RDFLAG command after the three-write-sequence,

validate the command counter (CC) incremented by 3.

Crash Signal Management

In case of a vehicle crash, it is typically required to do an

emergency disconnect of the HV battery from the vehicle's HV

network through firing the pyrofuse(s).

The BMS controller can command the ADBMS2950B devices

to activate the OCA and OCB outputs by setting the thresholds

of all three overcurrent ADCs to zero, or by inverting the OCA

and OCB outputs through OCAX, OCBX, and setting the

thresholds of all three overcurrent ADCs to the maximum. The

deglitch setting OCDGT must be set to the minimum value and

the OCDP must be activated for minimum latency (reduced

interval) between the rising edge of OCEN and the assertion of

the OCA, OCB output pins.

As described in the section Overcurrent Configuration Update,

three write commands are required to trigger the ignition from

the overcurrent function active state (OCEN = 1):

1. Send WRCFGB command to modify the OCxTH,

OCAX, OCBX, OCDGT, and OCDP bits as required.

2. Send WRCFGA command to clear OCEN bit. This

disables the overcurrent function and OCA, OCB pin

output drivers shortly.

3. Wait for tOCEN,DLY1 (no wait if tOCEN,DLY1 ≤ 0).

4. Send WRCFGA command to set the OCEN bit again.

When the ADSBM2950 derivative is configured in isoSPI mode

and the isoSPI is implemented in a redundant ring topology, the

device responds to commands irrespective of whether they are

received through isoSPI Port A or Port B. This allows the BMS

controller to send the above sequence redundantly to Port A

and Port B, thereby reducing he potential risk of command loss.

Successful OCx assertion can be confirmed through reading

back the OCAL and OCBL latch bits.

Most applications can also measure the voltage at the pyrofuse

output directly to verify the successful ignition.

Note that whenever OCEN is cleared, the OCx pins have a high

impedance state, which allows the pin state to be defined

through external pull-up or pull-down resistors. Figure 40

shows the expected timing of the OCx assertion for the PWM1

mode with OCAX = 0, OCBX = 0, COD = 0, OCDGT = 0,

OCDP = 1.

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