ADBMS2950BCCSZ datasheet(10/97 Pages) AD

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ADBMS2950B

Data Sheet

Rev. 0 | Page 10 of 97

SPI SPECIFICATIONS

Operating junction temperature (TJ) = −40°C to +125°C, VDD = 12V, VREG = 5.0V. ISOMD pin is connected low, unless otherwise noted.

Table 14. SPI Interface Specifications

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIGITAL OUTPUT VOLTAGE

Pin SDO

Low (VOL,SDO)

0.3

Pin SDO sinking 4 mA

DIGITAL INPUT VOLTAGE

Pins CSB, SCK, SDI, and ISOMD

High (VIH)

2.3

Low (VIL)

1.2

DIGITAL INPUT CURRENT

Pins SDI, ISOMD

µA

Pins CSB, SCK

µA

Pin voltage = 5V, ISOMD = 0

Pins CSB, SCK

µA

Pin voltage = 3.5V, ISOMD = 0

TIMINGS

SCK Period (tCLK)1

0.5

µs

SDI Setup Time before SCK Rising Edge

(t1)

SDI Hold Time after SCK Rising Edge (t2)

100

SCK Low (t3)

100

tCLK = t3 + t4 ≥ 0.5 µs

SCK High (t4)

100

tCLK = t3 + t4 ≥ 0.5 µs

CSB Rising Edge to CSB Falling Edge (t5)

µs

CSB Rising Edge to SDO Rising (t11)2

200

SCK Rising Edge to CSB Rising Edge (t6)1

0.5

µs

CSB Falling Edge to SCK Rising Edge (t7)1

0.5

µs

SCK Falling Edge to SDO Valid (t8)2

These timing specifications are dependent on the delay through the cable and include allowances for 50 ns of delay in each direction. A value of 50 ns corresponds to

10 meters of CAT5 cable (which has a velocity of propagation of 66% the speed of light). The use of longer cables requires derating these specifications by the amount

of additional delay.

These timing specifications do not include rise or fall time of SDO. Although fall time (which is typically 5 ns due to the internal pull-down transistor) is not a concern,

the rising edge transition time, tRISE, is dependent on the pull-up resistance and load capacitance on the SDO pin. The time constant must be chosen such that SDO

meets the setup time requirements of the BMS controller.

Figure 2. Timing Diagram of 4-Wire SPI

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