ADBMS2950BCCSZ datasheet(15/97 Pages) AD

15 / 97 page

Data Sheet

ADBMS2950B

Rev. 0 | Page 15 of 97

Pin No.

Mnemonic

Type

Description

45, 43

VREF1, VREF2

REF

Primary (VREF1 = 3.2V typ) and Secondary (VREF2 = 3.0V typ) Reference Voltage Outputs. Bypass each pin with a 1 μF (or

greater) capacitor to the PCB ground plane. Avoid common power ground paths between this capacitor's ground

connection and the SGND and RGND pin connections by placement of components and optional slots in the ground

plane. No DC loads are allowed on those pins.

VREF1P25

REF

Buffered Reference Voltage Output of 1.25V for driving 10 kΩ Thermistors and Resistor-Dividers. Bypass with a 1 μF

capacitor to the PCB ground plane. Avoid common power ground paths between this capacitor's ground connection and

the SGND pin connection by placement of components and optional slots in the ground plane.

5, 9

S1A, S2A

For more details, see the Current Sense Inputs section. Connect to PCB ground plane if current sense functionality is

unused.

3, 4, 7, 8

I1A, I1B, I2A,

I2B

Current and Overcurrent Sense Channel 1/2 Differential Signal Inputs (A: positive, B: negative). For more details, see the

Current Sense Inputs section. Connect to the PCB ground plane if current sense functionality is unused.

1, 11

I3A, I3B

Overcurrent Sense Channel 3 Differential Signal Inputs (A: positive, B: negative). For more details, see the Current Sense

Inputs section. Connect to the PCB ground plane if current sense functionality is unused.

48, 2, 10, 18,

6, 16

V1, V2, V3, V4,

V5, V6

Voltage Sense Inputs. Pins are internally buffered before being applied to V1ADC and V2ADC to ensure high input

impedance and low leakage. Leave floating or connected to the PCB ground plane (preferred) if unused.

12, 14

VBAT1, VBAT2

Battery Voltage Sense Inputs. VBAT1 and VBAT2 are internally buffered before being applied to VB1ADC and VB2ADC to

ensure high input impedance and low leakage. The VBxADC's inputs are configurable between either both differentially

VBAT1 to VBAT2 or individual single ended VBAT1 vs. SGND through VB1ADC and VBAT2 vs. SGND through VB2ADC.

Leave floating or connected to the PCB ground plane (preferred) if unused.

17, 13

V7, V8

Voltage Sense Inputs. Pins are internally buffered before being applied to V1ADC to ensure high input impedance and

low leakage. Input pins V7, V9 and V8, V10 each can form one redundant input pin-pair. Leave floating or connected to

the PCB ground plane (preferred) if unused.

19, 20

V9, V10

Voltage Sense Inputs. Pins are internally buffered before being applied to V2ADC to ensure high input impedance and

low leakage. Input pins V7, V9 and V8, V10 each can form one redundant input pin-pair. Leave floating or connected to

the PCB ground plane (preferred) if unused.

28, 29, 30, 31

GPIO1, GPIO2,

GPIO3, GPIO4

General-Purpose Inputs and Outputs (GPIOs). Pins can be used as digital inputs or digital outputs (open drain). Pins are

high impedance during power down and by default after power up/reset. GPIO3 (SDA) and GPIO4 (SCL) can be used as an

I2C controller port. GPIO1 (SDIM), GPIO2 (CSBM), GPIO3 (SDOM), and GPIO4 (SCKM) can be used as an SPI controller port.

Shared data-in/-out (SDIOM) through GPIO3 only (3-wire SPI, see bit SPI3W in CFGA) is also possible, allowing GPIO1 to be

used for other functions, for example, as a fault Output. Leave floating or connected to the PCB ground plane (preferred) if

unused.

32, 33, 34, 35,

37, 39

GPO1, GPO2,

GPO3, GPO4,

GPO5, GPO6

General-Purpose Outputs (GPOs). It can be configured individually for open-drain and push-pull mode. In push-pull mode,

the pin can be switched to GND or VDD. It can be used as an input when configured in open-drain mode with output

disabled. Dual threshold confirms whether the pin is at high or at low level. Pins are high impedance during power down,

and as default after power up/reset. GPO6 can be configured to a push-pull clock output with frequency 0.1 × OSC1.

Leave the pins floating if unused.

36, 38

OCA, OCB

Overcurrent Alert Push-Pull or Open Drain Outputs A/B with Programmable Polarity and PWM or Static Operation Mode.

State of the pins can be readback (OCAP, OCBP). In push-pull the pins can switch to VREG. Leave floating if unused.

ISOMD

isoSPI Mode Enable Input. Serial interface mode digital input. Connecting ISOMD to logic high level (VREG) configures

pins SDO, SCK/IPA, CSB/IMA, and SDI for 2-wire isolated SPI (isoSPI) mode. Connecting ISOMD to logic low level (GND)

configures the pins for 4-wire SPI mode.

SDO

4-Wire SPI Serial-Data Open-Drain Output (SDO) when ISOMD is Connected Low (GND). Pull-up resistor must be

connected externally (see VOL,SDO specification on SDO pin, which limits the minimum pull-up resistance). Connect to the

PCB ground plane when 2-wire isolated SPI mode is configured through ISOMD connected high.

SDI

4-Wire SPI Serial-Data Input (SDI) when ISOMD is Connected Low (GND). Connect to the PCB ground plane when 2-wire

isolated SPI mode is configured through ISOMD connected high.

SCK/IPA

4-Wire SPI Serial-Clock Input (SCK) or Differential Positive Input/Output Port A (IPA). The function of this pin depends on

the connection of ISOMD. When ISOMD is connected low, the SCK function is active. When ISOMD is connected high, the

IPA function is active.

CSB/IMA

4-Wire SPI Active Low Chip-Select input (CSB) or Differential Negative Input/Output Port A (IMA). The function of this pin

depends on the connection of ISOMD. When ISOMD is connected low, the CSB function is active. When ISOMD is

connected high, the IMA function is active.

22, 23

IPB, IMB

Differential (IPB: Plus, IMB: Minus) Input/Output Pins of the Isolated 2-wire SPI Port B. When ISOMD is connected to logic

low level (GND), the Port B operates in the controller mode only, and communication can only be initiated on the A-port

and never on the B-port. Termination resistor must be connected externally, or the pins can be connected to the PCB

ground plane if unused.

EPAD

N/A

Exposed Pad. Connect exposed pad to GND. The exposed pad is internally connected to GND. It must be connected to the

PCB ground plane through several vias. For more details, see the Current Sense Layout Recommendation and Footprint

Recommendation sections.

ADBMS2950BCCSZ 数据表(PDF) 15 Page - Analog Devices

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