ADBMS2950BCCSZ datasheet(20/97 Pages) AD

20 / 97 page

ADBMS2950B

Data Sheet

Rev. 0 | Page 20 of 97

communication data throughput by simultaneous split-chain

transactions.

Configurable isoSPI Break

Individual ADBMS2950B devices in a daisy-chain can be

configured to halt any transmission of data on the controller

isoSPI port. Perform this action by writing the COMMBK bit to

1 in CFGA. Asserting the COMMBK bit does not prevent the

IC from receiving and responding to commands from either

Port A or Port B. Therefore, this setup is useful in a reversible

isoSPI daisy-chain to increase the effective communication

bandwidth by splitting the chain in two. This is done by

asserting the COMMBK bits in the two center devices in the

daisy-chain. Then, the host can simultaneously issue commands

to both ends of the daisy-chain as if communicating to two

separate daisy-chains.

If a communication fault occurs while some devices are

configured for communication break, the host can successively

attempt to clear COMMBK in all the devices in the chain, and

in both the forward and reverse directions. This allows the host

access to all possible devices for identifying the location of the

communication fault.

It is also recommended to set the COMMBK bit in case the Port

B is not used to lower the VREG supply current consumption.

isoSPI Pulse Detail

Two ADBMS devices can communicate by transmitting and

receiving differential pulses back and forth through an isolation

barrier. The transmitter can output three voltage levels: +VA,

0V, and −VA. A positive output results from IP sourcing current

and IM sinking current across the load resistor. A negative

voltage is developed by IP sinking and IM sourcing. When both

outputs are off, the load resistance forces the differential output

to 0V.

To eliminate the DC signal component and enhance reliability,

isoSPI pulses are defined as symmetric pulse pairs. A +1 pulse is

transmitted as a positive pulse followed by a negative pulse. A

−1 pulse is transmitted as a negative pulse followed by a positive

pulse. The duration of each pulse is defined as t½PW because

each is half of the required symmetric pair (the total isoSPI

pulse duration is 2 × t½PW).

Table 21. isoSPI Pulse Types

Pulse Type

First Level (t½PW)

Second Level (t½PW)

Ending Level

Long +1

+VA (150 ns)

−VA (150 ns)

Long −1

−VA (150 ns)

+VA (150 ns)

Short +1

+VA (50 ns)

−VA (50 ns)

Short −1

−VA (50 ns)

+VA (50 ns)

A BMS controller does not have to generate isoSPI pulses to use

this 2-wire interface. The first ADBMS device in the system can

communicate to the BMS controller using the 4-wire SPI on its

Port A, then daisy-chain to other devices using the 2-wire

isoSPI on its Port B. Alternatively, the ADBMS6821 or

ADBMS6822 can be used to translate the SPI signals into isoSPI

pulses.

When the ADBMS device is operating with Port A configured

as an SPI controller, the SPI detects one of four communication

events: CSB falling, CSB rising, SCK rising with SDI = 0, and

SCK rising with SDI = 1. Each event is converted into one of

four pulse types for transmission to another daisy-chained

ADBMS device. Long pulses are used to transmit CSB changes,

and short pulses transmit data.

Table 22. Port B (Controller) isoSPI Port Function

Communication Event (Port A SPI)

Transmitted Pulse (Port B isoSPI)

CS Rising

Long +1

CS Falling

Long −1

SCK Rising Edge, SDI = 1

Short +1

SCK Rising Edge, SDI = 0

Short −1

On the other side of the isolation barrier (that is, at the other

end of the cable), the second ADBMS device has Port A

configured to isoSPI. It receives each transmitted pulse and

reconstructs the SPI signals internally, as shown in Table 23. In

addition, during a read command, this port can transmit return

data pulses.

The peripheral isoSPI port never transmits long (CSB) pulses. A

peripheral isoSPI port transmits short −1 pulse, or short +1

pulse when reading back a data bit. If the controller port

receives a null response rather than a short +1 pulse or a short

−1 pulse, the controller port recognizes the null response as

Logic 1 bit.

Table 23. Port A (Peripheral) isoSPI Port Function

Received Pulse (Peripheral isoSPI Port)

Internal SPI Port Action

Return Pulse

Long +1

Drive CSB high

None.

Long −1

Drive CSB low

None.

Short +1

Set SDI = 1

Short −1 pulse if reading 0 bit.

Pulse SCK

Short +1 pulse if reading 1 bit.

No return pulse if not in read mode.

Short −1

Set SDI = 0

Short -1 pulse if reading 0 bit.

Pulse SCK

Short +1 pulse if reading a 1 bit.

No return pulse if not in read mode.

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