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ADBMS2950BCCSZ 数据表(PDF) 49 Page - Analog Devices

部件名 ADBMS2950BCCSZ
功能描述  Battery Pack Monitor
PDF  97 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADBMS2950BCCSZ 数据表(HTML) 49 Page - Analog Devices

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Data Sheet
ADBMS2950B
Rev. 0 | Page 49 of 97
Registers and bits that are subject to the snap, unsnap protocol
are marked with FRZ in the Type column of the register and bit
descriptions. For more details on the operation of the snap,
unsnap commands, see the Snapshot Commands section.
CONFIGURATION AND STATUS
Configuration, status and flag register read, and write and clear
commands are listed in Table 66.
Fault and status information are read from the FLAG register
through RDFLAG. The CLRFLAG command is used to reset
individual bits in the FLAG register. Such as any write
command, the CLRFLAG command requires the system to
send six data bytes followed by the PEC per device. Any bit of
the data that is set (1) clears the related flag. The bits that are
cleared (0) do not affect the related flags.
Table 66. Configuration and Status Command Codes
Name
Type
BIT
10
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
Description
WRCFGA
WR48
0
0
0
0
0
0
0
0
0
0
1
Write CFGA register (ADBMS6830B: WRCFGA).
RDCFGA
RD48
0
0
0
0
0
0
0
0
0
1
0
Read CFGA register (ADBMS6830B: RDCFGA).
WRCFGB
WR48
0
0
0
0
0
1
0
0
1
0
0
Write CFGB register (ADBMS6830B: WRCFGB).
RDCFGB
RD48
0
0
0
0
0
1
0
0
1
1
0
Read CFGB register (ADBMS6830B: RDCFGB).
RDFLAG
RD48
0
0
0
0
ERR
1
1
0
0
1
0
Read FLAG register (ADBMS6830B: RDSTATC).
CLRFLAG
WR48
1
1
1
0
0
0
1
0
1
1
1
Write 1 to Clear Flag register Latches (ADBMS6830B:
CLRFLAG).
RDSTAT
RD48
0
0
0
0
0
1
1
0
1
0
0
Read STAT register (ADBMS6830B: RDSTATE).
RDALLC
RD160
0
0
0
0
0
0
1
0
0
0
0
Read All configuration, flag and status registers.
RDSID
RD48
0
0
0
0
0
1
0
1
1
0
0
Read SID register (ADBMS6830B: RDSID).
RDALL commands are not available on the isoSPI daisy-chains.
For more details, see the Communication Protocol section.
Table 67. RDFLAG Parameter Bits
Name
Type
Value
Description
ERR
PAR
SPIFLT Diagnostic Enable.
0
RDFLAG readout without artificial error injection.
1
RDFLAG readout with error injection.
Table 68 lists special control command codes used to reset the
IC (SRST), reset the command counter (RSTCC) and to control
the freeze mechanism that allows coherent data reading from
single ICs and multiple ICs in a daisy-chain (for more details,
see the Snapshot Commands section).
Table 68. Other Control Command Codes
Name
Type
BIT
10
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
Description
SRST
CMD
0
0
0
0
0
1
0
0
1
1
1
Software reset, including CCNT reset (ADBMS6830B:
SRST).
RSTCC
CMD
0
0
0
0
0
1
0
1
1
1
0
Reset command counter (ADBMS6830B: RSTCC).
SNAP
CMD
0
0
0
0
0
1
0
1
1
0
1
Freeze result registers (ADBMS6830B: SNAP).
UNSNAP
CMD
0
0
0
0
0
1
0
1
1
1
1
Unfreeze result registers (ADBMS6830B: UNSNAP).
The ADBMS2950B features two 48-bit registers for static
configuration. They are written by the WRCFGA and
WRCFGB commands and read by the RDCFGA and RDCFGB
commands, respectively. The configuration registers CFGA and
CFGB are implemented redundantly. Bit failure triggers SPIFLT
when SPI reads the registers back. Writes to these register
groups increment the command counter.
Table 69. CFGA Register Map
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
OCEN
VS5
VS4
VS3
VS2[1:0]
VS1[1:0]
1
INJTM
INJECC
0
INJTS
INJMON[1:0]
INJOSC[1:0]
2
SOAK
VS10
VS9
VS8
VS7
VS6
3
0
GPO6C[1:0]
GPO5C
GPO4C
GPO3C
GPO2C
GPO1C
4
SPI3W
GPIO1FE
GPO6OD
GPO5OD
GPO4OD
GPO3OD
GPO2OD
GPO1OD



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