PIC18F258-ESLASHSOSQTP datasheet(104/402 Pages) MICROCHIP

104 / 402 page

PIC18FXX8

DS41159E-page 102

9.4

PORTD, TRISD and LATD

Registers

PORTD is an 8-bit wide, bidirectional port. The corre-

sponding Data Direction register for the port is TRISD.

Setting a TRISD bit (= 1) will make the corresponding

PORTD pin an input (i.e., put the corresponding output

driver in a high-impedance mode). Clearing a TRISD

bit (= 0) will make the corresponding PORTD pin an

output (i.e., put the contents of the output latch on the

selected pin).

Read-modify-write operations on the LATD register

read and write the latched output value for PORTD.

PORTD uses Schmitt Trigger input buffers. Each pin is

individually configurable as an input or output.

PORTD can be configured as an 8-bit wide, micro-

processor port (Parallel Slave Port or PSP) by setting

the control bit PSPMODE (TRISE<4>). In this mode,

the input buffers are TTL. See Section 10.0 “Parallel

Slave Port” for additional information.

PORTD is also multiplexed with the analog comparator

module and the ECCP module.

EXAMPLE 9-4:

INITIALIZING PORTD

FIGURE 9-9:

PORTD BLOCK DIAGRAM IN I/O PORT MODE

Note:

This

port

only

available

the

PIC18F448 and PIC18F458.

CLRF

PORTD

; Initialize PORTD by

; clearing output

; data latches

CLRF

LATD

; Alternate method

; to clear output

; data latches

MOVLW

07h

; comparator off

MOVWF

CMCON

MOVLW

0CFh

; Value used to

; initialize data

; direction

MOVWF

TRISD

; Set RD3:RD0 as inputs

; RD5:RD4 as outputs

; RD7:RD6 as inputs

PORT/PSP Select

Data Bus

WR LATD

WR TRISD

Data Latch

TRIS Latch

RD TRISD

VDD

Vss

RD PORTD

RD0/PSP0/

PORTD

RD LATD

Schmitt

Trigger

Note

1: I/O pins have diode protection to VDD and VSS.

PSP Data Out

PSP Write

PSP Read

C1IN+

C1IN+ pin(1)

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