 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
PIC18F258-E/SOSQTP 数据表(PDF) 126 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC18F258-E/SOSQTP 数据表(HTML) 126 Page - Microchip Technology |
|
|
126 / 402 page  PIC18FXX8 DS41159E-page 124 © 2006 Microchip Technology Inc. 15.1 CCP1 Module Capture/Compare/PWM Register1 (CCPR1) is com- prised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. Table 15-1 shows the timer resources of the CCP module modes. TABLE 15-1: CCP1 MODE – TIMER RESOURCE 15.2 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16- bit value of the TMR1 or TMR3 register when an event occurs on pin RC2/CCP1. An event is defined as: • every falling edge • every rising edge • every 4th rising edge • every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit, CCP1IF (PIR registers), is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value will be lost. 15.2.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. 15.2.2 TIMER1/TIMER3 MODE SELECTION The timers used with the capture feature (either Timer1 and/or Timer3) must be running in Timer mode or Syn- chronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer used with each CCP module is selected in the T3CON register. TABLE 15-2: INTERACTION OF CCP1 AND ECCP1 MODULES CCP1 Mode Timer Resource Capture Compare PWM Timer1 or Timer3 Timer1 or Timer3 Timer2 Note: If the RC2/CCP1 is configured as an out- put, a write to the port can cause a capture condition. CCP1 Mode ECCP1 Mode Interaction Capture Capture TMR1 or TMR3 time base. Time base can be different for each CCP. Capture Compare The compare could be configured for the special event trigger which clears either TMR1 or TMR3, depending upon which time base is used. Compare Compare The compare(s) could be configured for the special event trigger which clears TMR1 or TMR3, depending upon which time base is used. PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt). PWM Capture None. PWM Compare None. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
