PIC18F258-ESLASHSOSQTP datasheet(123/402 Pages) MICROCHIP

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DS41159E-page 121

PIC18FXX8

14.2

Timer1 Oscillator

The Timer1 oscillator may be used as the clock source

for Timer3. The Timer1 oscillator is enabled by setting

the T1OSCEN bit (T1CON register). The oscillator is a

low-power oscillator rated up to 50 kHz. Refer to

Section 12.0 “Timer1 Module” for Timer1 oscillator

details.

14.3

Timer3 Interrupt

The TMR3 register pair (TMR3H:TMR3L) increments

from 0000h to 0FFFFh and rolls over to 0000h. The

TMR3 interrupt, if enabled, is generated on overflow

which is latched in interrupt flag bit TMR3IF (PIR regis-

ters). This interrupt can be enabled/disabled by setting/

clearing TMR3 Interrupt Enable bit, TMR3IE (PIE

registers).

14.4

Resetting Timer3 Using a CCP

Trigger Output

If the CCP module is configured in Compare mode

generate

“special

event

trigger”

(CCP1M3:CCP1M0 = 1011), this signal will reset

Timer3.

Timer3 must be configured for either Timer or Synchro-

nized Counter mode to take advantage of this feature. If

Timer3 is running in Asynchronous Counter mode, this

Reset operation may not work. In the event that a write

to Timer3 coincides with a special event trigger from

CCP1, the write will take precedence. In this mode of

operation, the CCPR1H:CCPR1L register pair becomes

the period register for Timer3. Refer to Section 15.0

“Capture/Compare/PWM (CCP) Modules” for CCP

details.

TABLE 14-1:

REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER

Note:

The special event triggers from the CCP

module will not set interrupt flag bit

TMR3IF (PIR registers).

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

GIE/ GIEH PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x 0000 000u

PIR2

—

CMIF

—

EEIF

BCLIF

LVDIF

TMR3IF

ECCP1IF -0-0 0000 -0-0 0000

PIE2

—

CMIE

—

EEIE

BCLIE

LVDIE

TMR3IE

ECCP1IE -0-0 0000 -0-0 0000

IPR2

—

CMIP

—

EEIP

BCLIP

LVDIP

TMR3IP

ECCP1IP -1-1 1111 -1-1 1111

TMR3L

Holding Register for the Least Significant Byte of the 16-bit TMR3 Register

xxxx xxxx uuuu uuuu

TMR3H

Holding Register for the Most Significant Byte of the 16-bit TMR3 Register

xxxx xxxx uuuu uuuu

T1CON

RD16

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

T3CON

RD16

T3ECCP1

T3CKPS1 T3CKPS0

T3CCP1

T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu

Legend:

= unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

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