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ICS1893CFILF 数据表(PDF) 110 Page - Integrated Circuit Systems |
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ICS1893CFILF 数据表(HTML) 110 Page - Integrated Circuit Systems |
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110 / 126 page  ICS1893CF, Rev. F, 03/01/07 Mar. 2007 110 Chapter 9 DC and AC Operating Conditions ICS1893CF Data Sheet - Release Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 9.5.8 10M Media Independent Interface: Receive Latency Table 9-15 lists the significant time periods for the 10M MII timing. The time periods consist of timings of signals on the following pins: • TP_RX (that is, the MII TP_RXP and TP_RXN pins) • RXCLK • RXD Figure 9-9 shows the timing diagram for the time periods. Figure 9-9. 10M MII Receive Latency Timing Diagram Table 9-15. 10M MII Receive Latency Time Period Parameter Conditions Min. Typ. Max. Units t1 First Bit of /5/ on TP_RX to /5/D/ on RXD 10M MII – 6.5 7 Bit times † Manchester encoding is not shown. 5 5 D 5 t1 TP_RX† RXCLK RXD |
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