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ICS1893CFILF 数据表(PDF) 113 Page - Integrated Circuit Systems |
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ICS1893CFILF 数据表(HTML) 113 Page - Integrated Circuit Systems |
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113 / 126 page  Chapter 9 DC and AC Operating Conditions ICS1893CF, Rev. F, 03/01/07 Mar. 2007 113 ICS1893CF Data Sheet Rev. F - Release Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 9.5.11 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-18 lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • CRS Figure 9-12 shows the timing diagram for the time periods. Figure 9-12. 100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) Table 9-18. 100M MII Carrier Assertion/De-Assertion (Half-Duplex Transmission Only) Time Period Parameter Condi- tions Min. Typ. Max. Units t1 TXEN Sampled Asserted to CRS Assert 0 3 4 Bit times t2 TXEN De-Asserted to CRS De-Asserted 0 3 4 Bit times t2 t1 TXEN TXCLK CRS |
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