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ICS1893CFILF 数据表(PDF) 111 Page - Integrated Circuit Systems |
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ICS1893CFILF 数据表(HTML) 111 Page - Integrated Circuit Systems |
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111 / 126 page ![]() Chapter 9 DC and AC Operating Conditions ICS1893CF, Rev. F, 03/01/07 Mar. 2007 111 ICS1893CF Data Sheet Rev. F - Release Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 9.5.9 10M Media Independent Interface: Transmit Latency Table 9-16 lists the significant time periods for the 10M MII transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • TXD (that is, TXD[3:0]) • TP_TX (that is, TP_TXP and TP_TXN) Figure 9-10 shows the timing diagram for the time periods. Figure 9-10. 10M MII Transmit Latency Timing Diagram Table 9-16. 10M MII Transmit Latency Timing Time Period Parameter Conditions Min. Typ. Max. Units t1 TXD Sampled to MDI Output of First Bit 10M MII – 1.2 2 Bit times TXCLK TXEN TXD † Manchester encoding is not shown. 55 5 t1 TP_TX† |
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