SC16C852LIB datasheet(36/60 Pages) PHILIPS

36 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

36 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

[1]

For 32-byte FIFO mode, refer to Section 7.3.

7.17 Flow Control Trigger Level High (FLWCNTH)

This 8-bit register is used to store the receive FIFO high threshold levels to start/stop

transmission during hardware/software ﬂow control. Table 29 shows FLWCNTH register

bit settings; see Section 6.5.

[1]

For 32-byte FIFO mode, refer to Section 7.3.

7.18 Flow Control Trigger Level Low (FLWCNTL)

This 8-bit register is used to store the receive FIFO low threshold levels to start/stop

transmission during hardware/software ﬂow control. Table 30 shows FLWCNTL register bit

settings; see Section 6.5.

[1]

For 32-byte FIFO mode, refer to Section 7.3.

7.19 Clock Prescaler (CLKPRES)

This register hold values for the clock prescaler.

Table 29.

FLWCNTH register bits description

Bit

Symbol

Description

7:0

FLWCNTH[7:0]

This register stores the programmable HIGH threshold level for

hardware and software ﬂow control for 128-byte FIFO mode[1].

0x00 = trigger level is set to 1

0x01 = trigger level is set to 1

...

0x80 = trigger level is set to 128

Table 30.

FLWCNTL register bits description

Bit

Symbol

Description

7:0

FLWCNTL[7:0]

This register stores the programmable LOW threshold level for

hardware and software ﬂow control for 128-byte FIFO mode[1].

0x00 = trigger level is set to 1

0x01 = trigger level is set to 1

...

0x80 = trigger level is set to 128

Table 31.

Clock Prescaler register bits description

Bit

Symbol

Description

7:4

CLKPRES[7:4]

reserved

3:0

CLKPRES[3:0]

Clock Prescaler value. Reset to 0.

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