SC16C852LIB datasheet(24/60 Pages) PHILIPS

24 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

24 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

7.1 Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

transmit FIFO. The THR empty ﬂag in the LSR will be set to a logic 1 when the transmit

FIFO is empty or when data is transferred to the TSR.

The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a

Receive Serial Shift Register (RSR). Receive data is removed from the SC16C852L

receive FIFO by reading the RHR. The receive section provides a mechanism to prevent

false starts. On the falling edge of a start or false start bit, an internal receiver counter

starts counting clocks at the 16

× clock rate. After 71⁄

2 clocks, the start bit time should be

shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a

logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from

assembling a false character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the INTA, INTB output pins.

Table 11.

Interrupt Enable Register bits description

Bit

Symbol

Description

IER[7]

CTS interrupt.

logic 0 = disable the CTS interrupt (normal default condition)

logic 1 = enable the CTS interrupt. The SC16C852L issues an interrupt when

the CTSA/CTSB pin transitions from a logic 0 to a logic 1.

IER[6]

RTS interrupt.

logic 0 = disable the RTS interrupt (normal default condition)

logic 1 = enable the RTS interrupt. The SC16C852L issues an interrupt when

the RTSA/RTSB pin transitions from a logic 0 to a logic 1.

IER[5]

Xoff interrupt.

logic 0 = disable the software ﬂow control, receive Xoff interrupt (normal

default condition)

logic 1 = enable the receive Xoff interrupt

IER[4]

Sleep mode.

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode

IER[3]

Modem Status Interrupt. This interrupt will be issued whenever there is a modem

status change as reﬂected in MSR[3:0].

logic 0 = disable the modem status register interrupt (normal default condition)

logic 1 = enable the modem status register interrupt

IER[2]

Receive Line Status interrupt. This interrupt will be issued whenever a receive

data error condition exists as reﬂected in LSR[4:1].

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

SC16C852LIB 数据表(PDF) 24 Page - NXP Semiconductors

SC16C852LIB 数据表(HTML) 24 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载