SC16C852LIB datasheet(12/60 Pages) PHILIPS

12 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

12 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

[1]

These registers are accessible only when LCR[7] is a logic 0.

[2]

These registers are accessible only when LCR[7] is a logic 1.

[3]

Second special registers are accessible only when EFCR[0] = 1.

[4]

Enhanced feature registers are only accessible when LCR = 0xBF.

[5]

First extra feature registers are only accessible when EFCR[2:1] = 01b.

[6]

Second extra feature registers are only accessible when EFCR[2:1] = 10b.

6.4 FIFO operation

6.4.1 32-byte FIFO mode

When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the

‘First extra feature register set’ are empty (0x00) the transmit and receive trigger levels are

set by FCR[7:4]. In this mode the transmit and receive trigger levels are backward

compatible to the SC16C652B (see Table 6), and the FIFO sizes are 32 entries. The

transmit and receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]).

It should be noted that the user can set the transmit trigger levels by writing to the FCR,

but activation will not take place until EFR[4] is set to a logic 1. The receiver FIFO section

includes a time-out function to ensure data is delivered to the external CPU (see

Section 6.8). Please refer to Table 13 and Table 14 for the setting of FCR[7:4].

6.4.2 128-byte FIFO mode

When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘ﬁrst extra feature

set by TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the

transmit FIFO, and the transmit trigger levels can be set to any value between 1 and 128

with granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive

trigger levels can be set to any value between 1 and 128 with granularity of 1.

When the effective FIFO size changes (that is, when FCR[0] toggles or when the

combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between

equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will

be lost).

Second extra feature register set (CLKPRES, RS485TIME, AFCR2, AFCR1)[6]

Clock Prescaler

RS-485 turn-around Timer

Additional Feature Control Register 2 Additional Feature Control Register 2

Additional Feature Control Register 1 Additional Feature Control Register 1

Table 5.

Internal registers decoding …continued

Read mode

Write mode

Table 6.

Interrupt trigger level and ﬂow control mechanism

FCR[7:6]

FCR[5:4]

INTA/INTB pin activation

Negate RTS or

send Xoff

Assert RTS or

send Xon

SC16C852LIB 数据表(PDF) 12 Page - NXP Semiconductors

SC16C852LIB 数据表(HTML) 12 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载