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SC16C852LIB 数据表(PDF) 39 Page - NXP Semiconductors |
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SC16C852LIB 数据表(HTML) 39 Page - NXP Semiconductors |
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39 / 60 page ![]() SC16C852L_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 25 January 2007 39 of 60 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 7.23 SC16C852L external reset condition and Software Reset These two reset methods are identical and will reset the internal registers as indicated in Table 35. Table 35. Reset state for registers Register Reset state IER IER[7:0] = 0 FCR FCR[7:0] = 0 ISR ISR[7:1] = 0; ISR[0] = 1 LCR LCR[7:0] = 0 MCR MCR[7:0] = 0 LSR LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0 MSR MSR[7:4] = input signals; MSR[3:0] = 0 EFCR EFCR[7:0] = 0 SPR SPR[7:0] = 1 DLL undefined DLM undefined TXLVLCNT TXLVLCNT[7:0] = 0 RXLVLCNT RXLVLCNT[7:0] = 0 EFR EFR[7:0] = 0 Xon1 undefined Xon2 undefined Xoff1 undefined Xoff2 undefined TXINTLVL TXINTLVL[7:0] = 0 RXINTLVL RXINTLVL[7:0] = 0 FLWCNTH FLWCNTH[7:0] = 0 FLWCNTL FLWCNTL[7:0] = 0 CLKPRES CLKPRES[7:0] = 0 RS485TIME RS485TIME[7:0] = 0 AFCR2 AFCR2[7:0] = 0 AFCR1 AFCR1[7:0] = 0 Table 36. Reset state for outputs Output Reset state TXA, TXB logic 1 OP2A, OP2B logic 1 RTSA, RTSB logic 1 DTRA, DTRB logic 1 INTA, INTB 3-state condition |
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