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SC16C852LIB 数据表(PDF) 48 Page - NXP Semiconductors

部件名 SC16C852LIB
功能描述  1.8 V dual UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
PDF  60 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

SC16C852LIB 数据表(HTML) 48 Page - NXP Semiconductors

Back Button SC16C852LIB Datasheet HTML 44Page - NXP Semiconductors SC16C852LIB Datasheet HTML 45Page - NXP Semiconductors SC16C852LIB Datasheet HTML 46Page - NXP Semiconductors SC16C852LIB Datasheet HTML 47Page - NXP Semiconductors SC16C852LIB Datasheet HTML 48Page - NXP Semiconductors SC16C852LIB Datasheet HTML 49Page - NXP Semiconductors SC16C852LIB Datasheet HTML 50Page - NXP Semiconductors SC16C852LIB Datasheet HTML 51Page - NXP Semiconductors SC16C852LIB Datasheet HTML 52Page - NXP Semiconductors Next Button
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SC16C852L_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 25 January 2007
48 of 60
NXP Semiconductors
SC16C852L
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
Fig 20. Receive ready timing in FIFO mode (16 mode)
D0
D1
D2
D3
D4
D5
D6
D7
002aac614
first byte that
reaches the
trigger level
stop
bit
parity
bit
td(stop-RXRDY)
RXA, RXB
RXRDYA, RXRDYB
IOR
active data
ready
start
bit
data bits (0 to 7)
active
td(IOR-RXRDYH)
Fig 21. Receive ready timing in FIFO mode (68 mode)
D0
D1
D2
D3
D4
D5
D6
D7
002aac621
first byte that
reaches the
trigger level
stop
bit
parity
bit
td(stop-RXRDY)
RXA, RXB
RXRDYA, RXRDYB
CS (read)
active data
ready
start
bit
data bits (0 to 7)
active
td(CS-RXRDYH)R



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