SC16C852LIB datasheet(16/60 Pages) PHILIPS

16 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

16 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

Programming the baud rate generator registers CLKPRES, DLM (MSB) and DLL (LSB)

provides a user capability for selecting the desired ﬁnal baud rate. The example in Table 7

shows the selectable baud rate table available when using a 1.8432 MHz external clock

input when MCR[7] = 0, and CLKPRES = 0x00.

Fig 6.

Crystal oscillator connection

If fXTAL1 frequency is greater than 50 MHz, then a DC blocking capacitor is required.

XTAL2 pin should be left unconnected when an external clock is used.

Fig 7.

External clock connection

Table 7.

Baud rate generator programming table using a 1.8432 MHz clock when

MCR[7] = 0 and CLKPRES[3:0] = 0

Output

baud rate

(bit/s)

Output

× clock divisor

(decimal)

Output

× clock divisor

(hexadecimal)

DLM

program value

(hexadecimal)

DLL

program value

(hexadecimal)

2304

900

1536

600

110

1047

417

150

768

300

384

180

600

192

1.2 k

2.4 k

3.6 k

4.8 k

7.2 k

9.6 k

19.2 k

002aaa870

47 pF

XTAL1

XTAL2

1.8432 MHz

22 pF

33 pF

XTAL1

XTAL2

1.5 k

Ω

1.8432 MHz

22 pF

002aac630

XTAL1

XTAL2

100 pF

fXTAL1

SC16C852LIB 数据表(PDF) 16 Page - NXP Semiconductors

SC16C852LIB 数据表(HTML) 16 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载

链接网址

SC16C852LIB 数据表(PDF) 16 Page - NXP Semiconductors

SC16C852LIB 数据表(HTML) 16 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表 下载

链接网址

数据表下载