SC16C852LIB datasheet(17/60 Pages) PHILIPS

17 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

17 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

6.10 DMA operation

The SC16C852L FIFO trigger level provides additional ﬂexibility to the user for block mode

operation. The user can optionally operate the transmit and receive FIFOs in the DMA

mode (FCR[3]). The DMA mode affects the state of the RXRDYA/RXRDYB and

TXRDYA/TXRDYB output pins. Table 8 and Table 9 show this.

[1]

Receive FIFO becomes full at 32 bytes when in normal mode. When TXINTLVL or RXINTLVL or FLWCNTH

or FLWCNTL contains any value other than 0x00 (extended mode), then the receive FIFO becomes full at

128 bytes.

[1]

Transmit FIFO becomes full at 32 bytes when in normal mode. When TXINTLVL or RXINTLVL or

FLWCNTH or FLWCNTL contains any value other than 0x00 (extended mode), then the transmit FIFO

becomes full at 128 bytes.

6.11 Loopback mode

The internal loopback capability allows on-board diagnostics. In the Loopback mode, the

normal modem interface pins are disconnected and reconﬁgured for loopback internally

(see Figure 8). MCR[3:0] register bits are used for controlling loopback diagnostic testing.

In the Loopback mode, the transmitter output (TX) and the receiver input (RX) are

disconnected from their associated interface pins, and instead are connected together

internally. The CTS, DSR, CD, and RI are disconnected from their normal modem control

input pins, and instead are connected internally to RTS, DTR, MCR[3] (OP2A/OP2B) and

MCR[2] (OP1A/OP1B). Loopback test data is entered into the transmit holding register via

the user data bus interface, D[7:0]. The transmit UART serializes the data and passes the

serial data to the receive UART via the internal loopback connection. The receive UART

converts the serial data back into parallel data that is then made available at the user data

interface D[7:0]. The user optionally compares the received data to the initial transmitted

data for verifying error-free operation of the UART TX/RX circuits.

In this mode, the interrupt pin is 3-stated, therefore, the software must use the polling

method (see Section 7.2.2) to send and receive data.

38.4 k

57.6 k

115.2 k

Table 7.

Baud rate generator programming table using a 1.8432 MHz clock when

MCR[7] = 0 and CLKPRES[3:0] = 0 …continued

Output

baud rate

(bit/s)

Output

× clock divisor

(decimal)

Output

× clock divisor

(hexadecimal)

DLM

program value

(hexadecimal)

DLL

program value

(hexadecimal)

Table 8.

Effect of DMA mode on state of RXRDYA/RXRDYB pin

Non-DMA mode

DMA mode

1 = FIFO empty

0-to-1 transition when FIFO empties

0 = at least 1 byte in FIFO

1-to-0 transition when FIFO reaches trigger level, or time-out

occurs[1]

Table 9.

Effect of DMA mode on state of TXRDYA/TXRDYB pin

Non-DMA mode

DMA mode

1 = at least 1 byte in FIFO

0-to-1 transition when FIFO becomes full[1]

0 = FIFO empty

1-to-0 transition when FIFO has at least one empty location

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