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SC16C852LIB 数据表(PDF) 22 Page - NXP Semiconductors |
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SC16C852LIB 数据表(HTML) 22 Page - NXP Semiconductors |
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22 / 60 page  xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 10. SC16C852L internal registers A2 A1 A0 Register Default[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W General register set[2] 0 0 0 RHR XX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R 0 0 0 THR XX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W 0 0 1 IER 00 CTS interrupt[3] RTS interrupt[3] Xoff interrupt[3] Sleep mode[3] modem status interrupt receive line status interrupt transmit holding register interrupt receive holding register interrupt R/W 0 1 0 FCR 00 RCVR trigger (MSB) RCVR trigger (LSB) TX trigger (MSB)[3] TX trigger (LSB)[3] DMA mode select XMIT FIFO reset RCVR FIFO reset FIFOs enable W 0 1 0 ISR 01 FIFOs enabled FIFOs enabled INT priority bit 4 INT priority bit 3 INT priority bit 2 INT priority bit 1 INT priority bit 0 INT status R 0 1 1 LCR 00 divisor latch enable set break set parity even parity parity enable stop bits word length bit 1 word length bit 0 R/W 1 0 0 MCR 00 clock select[3] IRDA enable reserved loopback OP2/INT enable (OP1) RTS DTR R/W 1 0 1 LSR 60 FIFO data error THR and TSR empty THR empty break interrupt framing error parity error overrun error receive data ready R 1 0 1 EFCR 00 reserved reserved reserved reserved reserved Enable extra feature bit 1 Enable extra feature bit 0 Enable TXLVLCNT/ RXLVLCNT W 1 1 0 MSR X0 CD RI DSR CTS ∆CD ∆RI ∆DSR ∆CTS R 1 1 1 SPR FF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W Special register set[4] 0 0 0 DLL XX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W 0 0 1 DLM XX bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 R/W Second special register Set[6] 0 1 1 TXLVLCNT 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W 1 0 0 RXLVLCNT 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W |
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