PPC440SPE datasheet(10/80 Pages) AMCC

10 / 80 page

PowerPC 440SPe Embedded Processor

AMCC Proprietary

Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

– 166MHz, maximum 5.2GB/s (simultaneous read and write)

– Processor vs Bus clock ratios of N:1 and N:2

•OPB

– Dynamic bus sizing: 32, 16, and 8-bit data path

– 32-bit address

– 83.33MHz, maximum 333MB/s

• DCR

– Register control bus

– 32-bit data path

– 10-bit address

On-Chip SRAM/L2 Cache

Features include:

• Four banks of 64KB each for a total of 256KB

• Configurable as either L2 cache or SRAM

• Memory cycles supported:

– Single beat read and write, 1 to 16 bytes

– Quadword Read and Write burst for 12-bit master

– Guarded memory accesses on 4KB boundaries

• Sustainable 2.6GB/s peak bandwidth at 166MHz

• Use as an L2 cache improves processor performance and reduces the PLB load

– Cache coherency maintained by a hardware snoop mechanism on the Low Latency (LL) PLB or by

software

– Data Array and Tag Array parity

– Unified data and instruction cache

– Four-way set associative

– 36-bit addressing

– Full LRU replacement algorithm

– Write through, look aside

• Use as Ethernet packet store allows Ethernet packets to be held for processing by the Ethernet core

PCI Express

Features include:

• Three independent PCI Express interfaces

– One 8 lanes

–Two 4 lanes

– 2.5 GB/sec full duplex per lane

• Compliant with PCI Express base specification 1.0a

• Each PCI Express port can be End Point or Root Complex. (Upstream & Downstream)

– Applications compliant with MSI rules are limited to one End Point port per PPC440SPe

• PCI-Express to PCI-Express opaque (Non-Transparent) bridge

• Power Management

• Supports one virtual channel (VC0) no Traffic Class (TC) filtering

• Maximum Payload block size 512 Bytes

• Supports up to 1024 byte maximum Read request size

• Requests supported:

– up to 4 posted outbound Write requests (memory and messages)

– up to 4 posted inbound Write requests

– up to 4 outbound Read requests outstanding on PCI Express

– up to 4 inbound Read requests outstanding on PCI Express

– Outbound I/O request as a PCI Express Root Port

– Inbound I/O request as a PCI Express End Point

PPC440SPE 数据表(PDF) 10 Page - Applied Micro Circuits Corporation

PPC440SPE 数据表(HTML) 10 Page - Applied Micro Circuits Corporation

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