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PPC440SPE 数据表(PDF) 68 Page - Applied Micro Circuits Corporation

部件名 PPC440SPE
功能描述  PowerPC 440SPe Embedded Processor
PDF  80 Pages
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制造商  AMCC [Applied Micro Circuits Corporation]
网页  http://www.amcc.com
标志 AMCC - Applied Micro Circuits Corporation

PPC440SPE 数据表(HTML) 68 Page - Applied Micro Circuits Corporation

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PowerPC 440SPe Embedded Processor
68
AMCC Proprietary
Revision 1.23 - Sept 21, 2006
Preliminary Data Sheet
EMCTxEn
na
na
15
2
19.1
8.7
EMCTxClk
EMCTxErr
na
na
15
2
19.1
8.7
EMCTxClk
Internal Peripheral Interface
IIC0SClk
n/a
n/a
n/a
n/a
15.3
10.2
IIC0SDA
-
-
-
-
15.3
10.2
IIC0SClk
IIC1SClk
n/a
n/a
n/a
n/a
15.3
10.2
IIC1SDA
-
-
-
-
15.3
10.2
IIC0SClk
UARTSerClk
n/a
n/a
n/a
n/a
19.1
8.7
UART0_Rx
-
-
n/a
n/a
-
-
UARTSerClk
UART0_Tx
n/a
n/a
-
-
19.1
8.7
UARTSerClk
UART0_DCD
-
-
n/a
n/a
19.1
8.7
async
UART0_DSR
-
-
n/a
n/a
19.1
8.7
async
UART0_CTS
-
-
n/a
n/a
19.1
8.7
async
UART0_DTR
n/a
n/a
19.1
8.7
async
UART0_RI
-
-
n/a
n/a
-
-
async
UART0_RTS
n/a
n/a
19.1
8.7
async
UART1_Rx
n/a
n/a
19.1
8.7
UARTSerClk
UART1_Tx
n/a
n/a
-
-
19.1
8.7
UARTSerClk
UART1_DSR/CTS
-
-
n/a
n/a
19.1
8.7
async
UART1_DTR/RTS
n/a
n/a
19.1
8.7
async
UART2_Rx
-
-
n/a
n/a
19.1
8.7
UARTSerClk
UART2_Tx
n/a
n/a
-
-
19.1
8.7
UARTSerClk
Interrupts Interface
IRQ0:15
-
-
-
-
n/a
n/a
async
JTAG Interface
TDI
-
-
na
na
na
na
async
TMS
-
-
nananana
async
TDO
na
na
-
-
19.1
8.7
async
TCK
-
-
nananana
async
TRST
-
-
na
na
na
na
async
System Interface
Halt
-
-
n/a
n/a
n/a
n/a
async
GPIO00:31
-
-
-
-
19.1
8.7
async
SysClk
-
-
n/a
n/a
n/a
n/a
na
SysErr
n/a
n/a
-
-
19.1
8.7
async
SysReset
-
-
-
-
n/a
n/a
async
HISRRst
-
-
-
-
19.1
8.7
async
TESTEN
-
-
n/a
n/a
n/a
n/a
async
TmrClk
-
-
n/a
n/a
n/a
n/a
na
Trace Interface
TrcClk
n/a
n/a
-
-
19.1
8.7
TRCBS0:2
-
-
-
-
19.1
8.7
TrcES0:4
-
-
-
-
19.1
8.7
TrcTS0:6
-
-
-
-
19.1
8.7
Table 14. I/O Specifications—All Speeds (Sheet 2 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133.33MHz. PCI-X input setup time requirement is 1.2ns for 133.33MHz
and 1.7ns for 66.66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66.66MHz. PCI output hold time
requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
3. These are DDR signals that can change on both the positive and negative clock transitions.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)



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