PPC440SPE datasheet(56/80 Pages) AMCC

56 / 80 page

PowerPC 440SPe Embedded Processor

AMCC Proprietary

Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

HISRRst

Hardware initiated system reset with an initial SDRAM

self-refresh phase to save data in Memory.

3.3V LVTTL

1, 2

TESTEN

Test Enable.

3.3V LVTTL

TMR_CLK

Processor timer external input clock.

3.3V LVTTL

JTAG Interface

TCK

Test Clock.

3.3V LVTTL

TDI

Test Data In.

3.3V LVTTL

w/pull-down

TDO

Test Data Out.

3.3V LVTTL

TMS

Test Mode Select.

3.3V LVTTL

with pull-up

TRST

Test Reset. During chip power-up, this signal must be

low from the start of VDD ramp-up until at least 16

SysClk cycles after VDD is stable in order to initialize the

JTAG controller.

3.3V LVTTL

with pull-up

Trace Interface

TrcClk

Trace data capture clock, runs at 1/4 the frequency of

the processor.

O3.3V LVTTL

TRCBS0:2

Trace branch execution status.

3.3V LVTTL

TrcES0:4

Trace Execution Status is presented every fourth

processor clock cycle.

O3.3V LVTTL

TrcTS0:6

Additional information on trace execution and branch

status.

O3.3V LVTTL

Tests

SCANOUT[00][07:08] [14:21] [25]

Test scan out

Manufacturing test signals: No need for termination

n/a

Power

PCIE0:2AV25

2.5V supply voltage for the serial link of the PCI Express

PCIE_PLLVDD2

2.5V supply voltage for the PCI Express Reference

clock Input receiver in front of the PLL

PCIE_PLLVDDA

Analog 2.5V filtered supply voltage A for the PLL of the

PCI Express

PCIE_PLLVDDB

Analog 2.5V filtered supply voltage B for the PLL of the

PCI Express

PCIE_PLLGNDA

GNDA for the PLL of the PCI Express

PCIE_PLLGNDB

GNDB for the PLL of the PCI Express

PCIX0PLLG

Ground for the PCI-X0 PLL

n/a

PCIX0PLLV

Analog 1.5V Filtered Supply voltages input for PCI-X0

A separate filter for all analog voltages is recommended.

In/a

Table 6. Signal Functional Description (Sheet 7 of 8)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3k

Ω to 3.3V)

3. Must pull down (recommended value is 1k

Ω)

4. If not used, must pull up (recommended value is 3k

Ω to 3.3V)

5. If not used, must pull down (recommended value is 1k

Ω)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

PPC440SPE 数据表(PDF) 56 Page - Applied Micro Circuits Corporation

PPC440SPE 数据表(HTML) 56 Page - Applied Micro Circuits Corporation

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PPC440SPE 数据表(PDF) 56 Page - Applied Micro Circuits Corporation

PPC440SPE 数据表(HTML) 56 Page - Applied Micro Circuits Corporation

Html Pages

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