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PPC440SPE 数据表(PDF) 49 Page - Applied Micro Circuits Corporation |
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PPC440SPE 数据表(HTML) 49 Page - Applied Micro Circuits Corporation |
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49 / 80 page ![]() PowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006 AMCC Proprietary 49 Preliminary Data Sheet Signal Description The PPC440SPe embedded controller is packaged in a 27mm Flip-Chip Plastic Ball Grid Array (FC-PBGA). The following tables describe the package level pinout. In the table “Signal Functional Description” on page 50, each I/O signal is listed along with a short description of its function. Active-low signals (for example, RAS) are marked with an overline. See “Signals Listed Alphabetically” on page 17 for the pin (ball) number to which each signal is assigned. Multiplexed Signals Some signals are multiplexed on the same pin so that the pin can be used for different functions. The signal names shown in Table 6 on page 50 are not accompanied by signal names that might be multiplexed on the same pin. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. Strapping Pins One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see “Strapping” on page 77). Note that these are not multiplexed pins since the function of the pins is not programmable. Multipurpose Signals In addition to multiplexing, some pins are also multi-purpose. For example, the PCIX0Ack can function instead as PCIX0ECC1 depending on the PCI interface mode of operation. Table 5. Pin Summary Group No. of Pins Total Signal Pins 495 AxVDD (1.5V) 3 AxVDD (2.5V HSS) 6 AxGND 5 OVDD (3.3V I/Os) 23 PxVDD (3.3/1.5V PCI) 14 SVDD (2.5/1.8V SDRAM) 14 VDD (1.5V logic) 28 GND 83 Total Power Pins Reserved 4 Total Pins 675 |
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