PPC440SPE datasheet(72/80 Pages) AMCC

72 / 80 page

PowerPC 440SPe Embedded Processor

AMCC Proprietary

Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

DDR SDRAM Write Operation

The following timing chart shows the relationship between the signals involved in a DDR write operation.

Figure 8. DDR SDRAM Write Cycle Timing

DDR SDRAM Read and Write I/O Timing—TSA and THA

Note 1: Clock speed is 333 MHz. TSA and THA are referenced to MemClkOut.

Note 2: Memory clock signal is shifted by 90

° from the internal clock.

Table 17. DDR SDRAM Read and Write I/O Timing—TSA and THA

Signal Name

TSA (ns)

THA (ns)

Minimum

MemAddr00:12

1.32

1.2

BA0:1

1.15

1.49

BankSel0:3

1.12

1.52

ClkEn0:3

1.29

1.45

CAS

1.24

1.14

RAS

1.29

1.48

1.35

1.43

DQS

MemData

PLB Clk

MemClkOut

Addr/Cmd

TSA

THA

TDS

TSD

THD

TSD

THD

TSA = Setup time for address and command signals to MemClkOut

THA = Hold time for address and command signals from MemClkOut

TDS = Delay from rising/falling edge of clock to the rising/falling edge of DQS

TSD = Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)

THD = Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)

PPC440SPE 数据表(PDF) 72 Page - Applied Micro Circuits Corporation

PPC440SPE 数据表(HTML) 72 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载