PPC440SPE datasheet(69/80 Pages) AMCC

69 / 80 page

PowerPC 440SPe Embedded Processor

Revision 1.23 - Sept 21, 2006

AMCC Proprietary

Preliminary Data Sheet

Table 15. I/O Specifications—667MHz

Notes:

1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.

Signal

Input (ns)

Output (ns)

Output Current (mA)

Clock

Notes

Setup Time

(TIS min)

Hold Time

(TIH min)

Valid Delay

(TOV max)

Hold Time

(TOH min)

I/O H

(minimum)

I/O L

(minimum)

External Slave Peripheral Interface

PerAddr00:26

n/a

6.2

19.1

8.7

PerClk

PerBE0:1

27.7

12.8

PerClk

PerBLast

n/a

5.7

n/a

19.1

8.7

PerClk

PerCS0:2

n/a

5.9

19.1

8.7

PerClk

PerData0:15

1.2

19.1

8.7

PerClk

PerOE

n/a

5.8

19.1

8.7

PerClk

PerPar0:1

1.7

5.7

n/a

19.1

8.7

PerClk

PerReady

3.6

n/a

19.1

8.7

PerClk

PerR/W

n/a

5.7

n/a

19.1

8.7

PerClk

PerWE

n/a

5.7

19.1

8.7

ExtReset

n/a

19.1

8.7

PerClk

n/a

19.1

8.7

PLB clk

PerErr

1.2

n/a

19.1

8.7

PerClk

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