PPC440SPE datasheet(52/80 Pages) AMCC

52 / 80 page

PowerPC 440SPe Embedded Processor

AMCC Proprietary

Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

PCIX0Req64/PCIX0ECC6

Request 64-bit transfer or ECC6.

Normally used by the current bus master to indicate a

64-bit transfer.

Used as ECC6 for PCIX0 mode 2.

I/O

3.3V PCI or

1.5V PCI for

mode 2

PCIX0Reset

Sets PCI device registers and logic to a consistent state.

3.3V PCI

PCIX0SErr

Reports address parity errors, data parity errors on the

Special Cycle command, or other catastrophic system

errors.

I/O

3.3V PCI

PCIX0Stop

Indicates the current target is requesting the master to

stop the current transaction.

I/O

3.3V PCI

PCIX0TRDY

Indicates the target agent’s ability to complete the

current data phase of the transaction.

I/O

3.3V PCI

PCIX0VC

Voltage control output. Used to control the voltage

regulator supplying the PCI I/O voltage. See PCIX0Cap

signal.

0 = 3.3V (PCI I/O)

1 =1.5V (PCI-X DDR)

3.3(1.5)V PCI

PCIX0VRef0:1

Voltage reference input for PCI-X mode 2/DDR (1.5V)

I/O. Not used for PCI or PCI-X mode 1.

VPCIXDDR

DDR SDRAM Interface

BA0:2

Bank Address supporting up to 8 internal banks.

2.5(1.8)V

DDR SDRAM

BankSel0:3

Selects up to four external DDR SDRAM banks.

2.5(1.8)V

DDR SDRAM

CAS

Column Address Strobe.

2.5(1.8)V

DDR SDRAM

ClkEn0:3

Clock Enable. One for each external bank.

2.5(1.8)V

DDR SDRAM

DM0:8

Memory write data byte lane masks. MEMDM8 is the

byte lane mask for the ECC byte lane.

2.5(1.8)V

DDR SDRAM

DQS0:8

Byte lane data strobe. DQS8 is the data strobe for the

ECC byte lane. These signals are differential pairs.

I/O

2.5(1.8)V

DDR SDRAM

DIFF

ECC0:7

ECC check bits 0:7.

I/O

2.5(1.8)V

DDR SDRAM

MemAddr14:00

Memory address bus.

Note:MemAddr14 is the most significant bit (msb).

2.5(1.8)V

DDR SDRAM

MemClkOut0:5

Subsystem clocks. The Clock signal (differential pair) is

duplicated six times to support high loading:

Six clocks can be used for two unbuffered DIMMS.

Each individual clock signal can be enabled by

programming the SDR0_DDRCLKSET register.

2.5(1.8)V

DDR SDRAM

DIFF

MemData63:00

Memory data bus.

Note:MemData63 is the most significant bit (msb).

I/O

2.5(1.8)V

DDR SDRAM

Table 6. Signal Functional Description (Sheet 3 of 8)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3k

Ω to 3.3V)

3. Must pull down (recommended value is 1k

Ω)

4. If not used, must pull up (recommended value is 3k

Ω to 3.3V)

5. If not used, must pull down (recommended value is 1k

Ω)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

PPC440SPE 数据表(PDF) 52 Page - Applied Micro Circuits Corporation

PPC440SPE 数据表(HTML) 52 Page - Applied Micro Circuits Corporation

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PPC440SPE 数据表(PDF) 52 Page - Applied Micro Circuits Corporation

PPC440SPE 数据表(HTML) 52 Page - Applied Micro Circuits Corporation

Html Pages

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数据表 下载

链接网址

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