PPC440SPE datasheet(63/80 Pages) AMCC

63 / 80 page

PowerPC 440SPe Embedded Processor

Revision 1.23 - Sept 21, 2006

AMCC Proprietary

Preliminary Data Sheet

Figure 4. Clock Timing Waveform

Spread Spectrum Clocking

Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440SPe. This controller

uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to

as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the

SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the

PPC440SPe the following conditions must be met:

• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the

PPC440SPe with one or more internal clocks at their maximum supported frequency, the SSCG can only lower

the frequency.

• The maximum frequency deviation cannot exceed -1%, and the modulation frequency cannot exceed 40kHz.

In some cases, on-board PPC440SPe peripherals impose more stringent requirements.

• Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks the

modulation.

• Use the DDR SDRAM MemClkOut since it also tracks the modulation.

Processor Clock (CPU Clock)

Frequency

400

666.66

MHz

Period

1.5

2.5

MemClkOut

Frequency

200

333.33

MHz

Period

TCH

High time

45% of nominal period

55% of nominal period

OPB Clock and PerClk

Frequency

–

83.33

MHz

Period

–

MAL Clock

Frequency

83.33

MHz

Period

22.2

Table 12. Clocking Specifications

Symbol

Parameter

Min

Max

Units

TCL

TCH

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