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M58PR512LE 数据表(PDF) 97 Page - STMicroelectronics |
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M58PR512LE 数据表(HTML) 97 Page - STMicroelectronics |
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97 / 119 page  M58PR256LE, M58PR512LE, M58PR001LE Common Flash interface 97/119 Table 47. Protection Register information Offset Data Description Value (P+E)h = 118h 0002h Number of protection register fields in JEDEC ID space. 0000h indicates that 256 fields are available. 2 (P+F)h = 119h 0080h Protection field 1: protection description Bits 0-7 Lower byte of protection register address Bits 8-15 Upper byte of protection register address Bits 16-23 2n bytes in factory pre-programmed region Bits 24-31 2n bytes in user programmable region 80h (P+10)h = 11Ah 0000h 00h (P+ 11)h = 11Bh 0003h 8 bytes (P+12)h = 11Ch 0003h 8 bytes (P+13)h = 11Dh 0089h Protection Register 2: protection description Bits 0-31 protection register address Bits 32-39 n number of factory programmed regions (lower byte) Bits 40-47 n number of factory programmed regions (upper byte) Bits 48-55 2n bytes in factory programmable region Bits 56-63 n number of user programmable regions (lower byte) Bits 64-71 n number of user programmable regions (upper byte) Bits 72-79 2n bytes in user programmable region 89h (P+14)h = 11Eh 0000h 00h (P+15)h = 11Fh 0000h 00h (P+16)h = 120h 0000h 00h (P+17)h = 121h 0000h 0 (P+18)h = 122h 0000h 0 (P+19)h = 123h 0000h 0 (P+1A)h = 124h 0010h 16 (P+1B)h = 125h 0000h 0 (P+1C)h = 126h 0004h 16 Table 48. Burst Read information Offset Data Description Value (P+1D)h = 127h 0005h Page-mode read capability bits 0-7 ’n’ such that 2n HEX value represents the number of read- page bytes. See offset 0028h for device word width to determine page-mode data output width. 32 bytes (P+1E)h = 128h 0003h Number of synchronous mode read configuration fields that follow. 3 (P+1F)h = 129h 0002h Synchronous mode read capability configuration 1 bit 3-7 Reserved bit 0-2 ’n’ such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device’s burstable address space. This field’s 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 0028h for word width to determine the burst data output width. 8 (P+20)h = 12Ah 0003h Synchronous mode read capability configuration 2 16 (P-21)h = 12Bh 0007h Synchronous mode read capability configuration 3 Cont. |
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