M58PR512LE datasheet(49/119 Pages) STMICROELECTRONICS

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M58PR256LE, M58PR512LE, M58PR001LE

Status Register

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6.8

Program Suspend Status bit (SR2)

The program suspend status bit indicates that a program operation has been suspended in

the addressed block. The program suspend status bit is onlyconsidered valid when the

Program/Erase Controller status bit is set to ‘1’ (Program/Erase Controller inactive).

When:

●

SR2 = 0, no Program/Erase Suspend command has been issued.

●

SR2 = 1, a Program/Erase Suspend command has been issued and the memory is

waiting for a Program/Erase Resume command.

SR2 is set within the program suspend latency time of the Program/Erase Suspend

command being issued, therefore, the memory may still complete the operation rather than

entering suspend mode.

When a Program/Erase Resume command is issued, the program suspend status bit is

reset to ‘0’.

6.9

Block protection status bit (SR1)

The block protection status bit dentifies if a program or block erase operation has tried to

modify the contents of a locked block.

When:

●

SR1 = 0, no program or erase operation has been attempted on a locked block.

●

SR1 = 1, a program or erase operation has been attempted on a locked block.

Once set to ‘1’, the block protection status bit must be cleared by a Clear Status Register

command or a hardware reset. This must be done before a new program or erase command

is issued, otherwise the new command appears to fail.

6.10

Bank write/multiple word program status bit (SR0)

The bank write status bit indicates if the addressed bank is programming or erasing.

The bank write status bit is only considered valid when the Program/Erase Controller status

bit SR7 is set to ‘0’.

When:

●

SR0 = 0 and SR7 = 0, the addressed bank is executing a program or erase operation.

●

SR0 = 1 and SR7 = 0, a program or erase operation is being executed in a bank other

than the one being addressed.

During buffer enhanced factory program operations the multiple word program bit, SR0,

shows if the device is ready to accept a new word to be programmed to the memory array.

When:

●

SR0 = 0, the device is ready for the next word.

●

SR0 = 1, the device is not ready for the next word.

For further details on how to use the Status Register, see the flowcharts and pseudocodes

provided in Appendix C.

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