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M58PR512LE 数据表(PDF) 10 Page - STMicroelectronics

部件名 M58PR512LE
功能描述  256-Mbit, 512-Mbit or 1-Gbit (횞 16, multiple bank, multilevel, burst) 1.8 V supply Flash memories
PDF  119 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M58PR512LE 数据表(HTML) 10 Page - STMicroelectronics

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Description
M58PR256LE, M58PR512LE, M58PR001LE
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The DPD (deep power-down) mode starts when the device is properly configured (ECR bit
15 is set) and the DPD signal is asserted. In DPD mode the device has the lowest power
consumption.
The M58PRxxxLE features an instant, individual block locking scheme that allows any block
to be locked or unlocked with no latency, enabling instant code and data protection. All
blocks have three levels of protection. They can be locked and locked-down individually
preventing any accidental programming or erasure. There is an additional hardware
protection against program and erase. When VPP ≤ VPPLK all blocks are protected against
program or erase. All blocks are locked at power-up.
In addition to the main memory array, the M58PRxxxLE features an extended flash array
(EFA) divided into 4 blocks of 64 Kbits each.
The EFA blocks are accessed through a separate set of commands. The operations
available in the EFA blocks are asynchronous read (in non-page mode), single word
program, erase and block locking. See Section 4: Command interface for details of the EFA
commands set.
See Table 5 for an extended flash array memory map. Table 19 and Table 20 describe the
simultaneous operations allowed in the EFA blocks and the main memory array.
The device includes 17 protection registers and 2 protection register locks, one for the first
protection register and the other for the 16 OTP (one-time-programmable) protection
registers of 128 bits each. The first protection register is divided into two areas: a 64-bit area
containing a unique device number written by ST, and a 64-bit area one-time-programmable
by the user. The user programmable area can be permanently protected. Figure 4, shows
the Protection Register memory map.
The memory is supplied with all the bits erased (set to ’1’).
Note:
The M58PRxxxLE memories are only available as part of a MCP (multichip package)
device.



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