M24C64-R datasheet(50/54 Pages) STMICROELECTRONICS

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Revision history

M24C64-W M24C64-R M24C64-F M24C64-DF

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DS6638 Rev 36

Revision history

Table 31. Document revision history

Date

Revision

Changes

14-Mar-2011

Updated information concerning E2, E1, E0 for the WLCSP package:

– note under Figure 3: UFDFPN5 package connections

– comment under Figure 7: Chip enable inputs connection

– note 3 under Table 2: Device select code

07-Apr-2011

Updated MLP8 package data and Section 10: Part numberingAdded

footnote (a) in Section 4.5: Memory addressing.

18-May-2011

Updated:

– Figure 3: UFDFPN5 package connections

– Table 6: Absolute maximum ratings

– Small text changes

Added:

– Figure 12: Memory cell characteristics

08-Sep-2011

Updated:

– Table 22: UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no

lead, 2 x 3 mm, data

– Figure 16: Maximum Rbus value versus bus parasitic capacitance

Cbus) for an I2C bus at maximum frequency fC = 1MHz

– Figure 6: I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value

versus bus parasitic capacitance (Cbus).

Added tWLDL and tDHWH in:

– Table 17: 400 kHz AC characteristics

– Table 18: 1 MHz AC characteristics

– Figure :

Minor text changes.

16-Dec-2011

Updated A dimension in Table 25: WLCSP- 5-bump, 0.959 x 1.073 mm,

0.4 mm pitch wafer level chip scale package mechanical data.

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