8.2

Suggested footprint

The STDRIVEG611 footprint for the PCB layout is usually defined based on several design factors such as

assembly plant technology capabilities and board component density. For easy device usage and evaluation,

STMicroelectronics provides the following footprint design, which is suitable for the largest variety of PCBs.

The following footprint indicates the copper area that should be free from the solder mask, while the copper area

could extend beyond the indicated areas for device pins, especially GND, PGND, and OUT pins, which is

beneficial for thermal and stray inductance minimization purposes.

A copper area connected to GND pins aids thermal dissipation, is useful to shield the input signal, and creates a

low inductance, good return path for supplying capacitor currents.

A copper area connected to PGND and OUT pins running below the related components can minimize gate loop

inductance for optimal gate driving and improves the return path for supply capacitor currents.

A PCB layout example is available with the STDRIVEG611 evaluation board.

Figure 19. QFN 4 x 5 x 1 mm, 18 leads, 0.5 mm pitch, suggested footprint

STDRIVEG611

Package information

DS14457 - Rev 2

page 26/33