AD4050BCPZ-R2 datasheet(32/67 Pages) AD

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Data Sheet

AD4050/AD4056

MODES OF OPERATION

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Rev. A | 32 of 67

AVERAGING MODE

In averaging mode, each rising edge of the CNV signal triggers a

conversion to start, and the averaging filter accumulates multiple

consecutive conversion results to generate a 14-bit averaged result.

Table 16 lists the configuration register settings to select averag-

ing mode. Figure 48 shows a typical connection diagram for the

AD4050/AD4056 digital interface that includes a recommended 200

Ω series resistor close to the CNV pin.

Figure 49 shows an interface timing diagram for averaging mode.

All timing specifications in Figure 49 are given in the Timing

Specifications section. The ADC sampling period (tCYC) is set by

the period of the CNV signal, and the output data rate (fODR) of

the averaging filter is fS divided by the averaging ratio (NAVG).

Larger averaging ratios yield greater noise reduction and resolution

improvements, but slower fODR. The averaging filter supports aver-

aging ratios from 2 to 256 and is set by the AVG_WIN_LEN bit field,

as described in the Block Averaging Filter section.

The digital host must wait for the averaged result to be ready before

asserting CS to start an SPI frame. The RDY signal acts as an

optional hardware interrupt to synchronize the SPI reads to the

ADC sampling phases (see the Data Ready Signal section). To

ensure optimal performance, the digital host must also observe the

tQUIET specification that defines the minimum delay between the

final SCLK falling edge and the next CNV rising edge.

By default, the averaging mode output data are 16-bits long, includ-

ing the 14-bit averaged ADC data with 2-bits of sign extension.

Averaging mode also offers an optional sign-extension byte and

CRC byte that can be appended to the 16-bit data. See the ADC

Mode Output Data Format section for details on the averaging

mode SDO data formatting options.

In averaging mode, the maximum sampling rate (fS) is limited by the

output data rate of the SPI (fODR), which is a function of the output

data length and serial clock frequency (fSCLK). See the Calculating

Serial Interface Output Data Rate section for details on estimating

the maximum achievable fS for the given operating conditions.

When the DEV_EN signal is enabled, the start of the conversion is

delayed by the programmable tPWR_ON delay, relative to the CNV

rising edge. See the Device Enable Signal section and Figure 52 for

specific timing details when using the DEV_EN signal.

Figure 48. Averaging Mode Example Connection Diagram

Figure 49. Averaging Mode Timing Diagram

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