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AD4050BCPZ-R2 数据表(PDF) 64 Page - Analog Devices

部件名 AD4050BCPZ-R2
功能描述  Compact, Low Power, 12-Bit, 2 MSPS/500 kSPS Easy Drive SAR ADC
PDF  67 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD4050BCPZ-R2 数据表(HTML) 64 Page - Analog Devices

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Data Sheet
AD4050/AD4056
REGISTER DETAILS
analog.com
Rev. A | 64 of 67
Table 48. Bit Descriptions for MIN_HYST_REG
Bits
Bit Name
Description
Reset
Access
7
RESERVED
Reserved.
0x0
R
[6:0]
MIN_HYST
Hysteresis Setting for Minimum Threshold. Sets the hysteresis setting for self-clearing the MIN_INTR signal
in monitor mode. Uses straight binary format.
0x0
R/W
MON_VAL SCALING REGISTER
Address: 0x2E to 0x2F, Reset: 0x0000, Name: MON_VAL_REG
Table 49. Bit Descriptions for MON_VAL_REG
Bits
Bit Name
Description
Reset
Access
[15:0]
MON_VAL
Gain Scaling Factor. Sets the scaling factor for ADC results when using MON_VAL scaling. MON_VAL can be
automatically generated or set manually. See the Gain Scaling and Achieving High Accuracy with Reference
Shutdown sections.
0x0
R/W
FUSE CRC REGISTER
Address: 0x40, Reset: 0x00, Name: FUSE_CRC
Table 50. Bit Descriptions for FUSE_CRC
Bits
Bit Name
Description
Reset
Access
[7:2]
RESERVED
Reserved.
0x0
R
1
FUSE_CRC_ERR
Fuse CRC Error Bit. Indicates an invalid fuse map CRC check. If this bit is set following the fuse map CRC
check, reset the device.
0x0
R/W1C
0
FUSE_CRC_EN
Fuse CRC Enable Bit. Setting this bit to 1 triggers a CRC check on the internal device fuse map. This bit
self-clears when the fuse map CRC check is complete.
0x0
R/W
DEVICE STATUS REGISTER
Address: 0x41, Reset: 0x40, Name: DEVICE_STATUS



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