AD4050BCPZ-R2 datasheet(40/67 Pages) AD

40 / 67 page

Data Sheet

AD4050/AD4056

SERIAL INTERFACE

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Rev. A | 40 of 67

Table 17. Status Word Contents

Status Word Index

Bit Field Name

NOT_RDY_ERR

SCLK_ERR

SPI_CRC_ERR

WR_INVALID

MB_ERR

ADDR_INVALID

DEVICE_READY

INTERFACE_ERR

FUSE_CRC_ERR

THRESH_OVERRUN

MAX_FLAG

MIN_FLAG

Data Phase

The data phase immediately follows the instruction phase. During

the data phase, register data is either clocked out on the SDO pin

(for register reads) or latched in on the SDI pin (for register writes).

Each configuration mode SPI frame can have one or multiple data

phases, as shown in Figure 63.

Each register address (REG_ADDR) corresponds to 1 byte of

multiple of 8 bits (8 SCLK periods) for the register read or write to

be considered valid. Registers are not updated if the register write

data phase is not an integer multiple of 8 bits.

The AD4050/AD4056 support bulk register reads and writes for

efficient access to contiguous sections of the register map. Figure

63 shows the SPI protocol for bulk register reads and writes. To

perform bulk read and write register transactions, hold the CS sig-

nal low and continue issuing SCLK pulses to execute multiple data

phases in succession. When streaming registers, the instruction

phase defines the REG_ADDR for the first data phase, and in each

subsequent data phase the address decrements by 1.

When the interface CRC is enabled, a CRC byte is appended for

each data phase byte (see the Register Access CRC section).

Figure 63. Streaming Registers in Configuration Mode

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