AD4050BCPZ-R2 datasheet(48/67 Pages) AD

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Data Sheet

AD4050/AD4056

APPLICATIONS INFORMATION

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Rev. A | 48 of 67

voltage, despite the charge transient from the AD4050/AD4056

REF pin, to prevent gain error or stuck bits in the conversion

results.

A reference decoupling capacitor (CREF) is strongly recommended

to supply the instantaneous charge drawn by the REF pin while

maintaining the VREF voltage to within an LSB. For optimal perform-

ance, populate CREF with a 2.2 μF capacitor with a case size of

0402 or larger to ensure suitable capacitor voltage coefficient. For

space-constrained applications, a 1 μF capacitor in a case size of

0201 may be used with slight degradation to gain error and INL.

Place the CREF capacitor on the same PCB layer and as close

to the REF pin as possible with a wide trace to minimize series

impedance (see the Layout Recommendations section).

While the AD4050/AD4056 is idling (not performing conversions),

the REF pin draws only a small standby current (8 nA). In applica-

tions where the AD4050/AD4056 intermittently switches between

idling and performing bursts of conversions (for example, when

using burst averaging mode), the IREF quickly shifts from near-zero

current to 60 μA/15 μA for fS = 2 MSPS/ 500 kSPS. This step

in load current triggers an output load transient response in the

reference circuit that must be considered if VREF varies by more

than ½ LSB. The MAX6070 voltage reference is recommended

for its exceptional transient response with low power dissipation.

Figure 72 illustrates the transient loading effects on the reference

circuit in response to a burst of conversions.

Figure 72. Burst Sampling and Voltage Reference Settling

Reference Noise Considerations

The voltage reference circuit noise is critical for achieving the sys-

tem-level dynamic range and SNR target specifications. For large

input signals near full scale, any noise from the reference circuit

will couple into the conversion results and modulate around the

fundamental frequency. Reference noise will also limit the SNR and

resolution improvements gained from using high averaging ratios in

averaging mode and burst averaging mode.

SYNCHRONIZED AMPLIFIER SHUTDOWN AND

ADC SAMPLING

The DEV_EN signal is an amplifier power-down signal generated

by the AD4050/AD4056 and synchronized to the ADC to maximize

amplifier power-up settling time prior to the sampling instant. Figure

41 shows a typical connection diagram when using the AD4050/

AD4056 DEV_EN signal with an operational amplifier. The DEV_EN

signal is assigned to the GP0 output pin in this example.

As described in the Device Enable Signal section, the DEV_EN

signal is asserted following the CNV signal rising edge to enable

the connected amplifier. The sampling instant is delayed until the

user-programmable tPWR_ON delay elapses. After the tPWR_ON delay

elapses, the DEV_EN signal is deasserted to power down the

amplifier. Consult the amplifier data sheet for its shutdown pin logic

levels to ensure compatibility with the AD4050/AD4056 logic levels

that are set by the VIO voltage and given in Table 1.

To ensure the amplifier output settles before the ADC sampling

instant, set the tPWR_ON delay to be longer than the amplifier turn-on

time specification. Turn-on time indicates the time needed for the

amplifier output to settle to a specified accuracy following assertion

of its ENABLE/SHUTDOWN input. Note that turn-on time varies

for different loads and amplifier configurations. The Introduction to

Dynamic Power Scaling article provides guidance on configuring

and evaluating operational amplifier power cycling relative to the

SAR ADC sampling.

See Figure 52 and Figure 54 for timing diagrams using DEV_EN in

the various AD4050/AD4056 operating modes.

ACHIEVING HIGH ACCURACY WITH

REFERENCE SHUTDOWN

Low-noise, high-accuracy voltage references are generally recom-

mended to pair with precision SAR ADCs to maximize system-level

performance. The voltage reference circuit also needs to have low

output impedance and fast transient response to deal with the

SAR ADC REF input transient load, especially when performing

bursts of samples (see the Reference Circuit Design section).

Low-power voltage references generally cannot satisfy all of these

requirements simultaneously, which often forces system designers

to add a reference buffer amplifier, increasing overall system power

dissipation.

The MAX6070 is an exceptionally low-power voltage reference that

can drive the AD4050/AD4056 REF pin directly without an inter-

mediate reference buffer amplifier. For extremely power-sensitive

applications, however, the AD4050/AD4056 offer unique features

that allow the voltage reference to be disabled without degrading

precision.

The AD4050/AD4056 can select the VDD supply as the VREF

source, as described in the Reference Selection Modes section.

To maintain accuracy while using VDD as the VREF, the AD4050/

AD4056 can directly measure the ratio between the VDD supply

and the REF input voltages and calculate a corresponding digital

correction factor to automatically scale the ADC samples according-

ly. The digital correction uses the MON_VAL field described in the

Gain Scaling section to scale the ADC transfer function between

the REF and VDD domains.

The automatic MON_VAL scaling calculation consist of two phases.

Figure 73 illustrates the AD4050/AD4056 configuration while meas-

uring and calculating the MON_VAL digital correction factor. Figure

74 shows the configuration after MON_VAL is updated and the

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