AD4050BCPZ-R2 datasheet(39/67 Pages) AD

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Data Sheet

AD4050/AD4056

SERIAL INTERFACE

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Rev. A | 39 of 67

The AD4050/AD4056 digital interface includes a 4-wire SPI for

serial data transfer, a CNV input for triggering ADC conversions,

and two general-purpose digital outputs, GP0 and GP1. The SPI

is primarily used for reading and writing the AD4050/AD4056 con-

figuration registers and for reading the ADC results. The Modes of

Operation section describe the SPI functionality and protocols for

each operating mode.

A 200 Ω series resistor is recommended between the AD4050/

AD4056 CNV pin and the digital host (see Figure 69). When

using pull-up or pull-down resistors on the digital traces, 100 kΩ is

recommended to minimize excess power dissipation.

The AD4050/AD4056 SPI follows clock polarity (CPOL) = clock

phase (CPHA) = 0 protocol, where the SCLK signal idles low, data

is latched on SDI on SCLK rising edge, and data is updated on

SDO on SCLK falling edge.

The AD4050/AD4056 include a CRC for register reads and writes

and ADC data reads supporting robust data transfers. The ADC

data are formatted to integer multiples of bytes to maximize com-

patibility with microcontroller internal memory transfer operations

such as direct memory access (DMA) transfers from the SPI to

the central processing unit (CPU). See the ADC Mode Output Data

Format section for details on CRC and sign extension.

The interface logic level is set by the VIO supply voltage, as

specified in Table 1. The AD4050/AD4056 support 1.8 V, 2.5 V, and

3.3 V logic systems. Note that the SPI timing specifications differ

between each operating mode and for different VIO logic levels

(see the Timing Specifications section).

CONFIGURATION MODE

Configuration mode is used to read and write to the user registers

that configure the AD4050/AD4056 operating modes and features.

Configuration mode is the default operating mode following pow-

er-up and device resets. In configuration mode, the digital host

accesses the user registers via the SPI, and the AD4050/AD4056

CNV input is ignored to prevent the ADC core from performing

unnecessary conversions. Register reads and writes are supported

only in configuration mode.

Figure 62 shows the data format for register reads and writes

in configuration mode. Register reads and writes consist of an

instruction phase followed by a data phase. The following sections

provide further details about each phase of register read and write

transactions.

Figure 62. Configuration Mode SPI Format

Instruction Phase

The instruction phase begins following each CS falling edge. There

is only one instruction phase per SPI frame, and the instruction

phase is followed by one or more data phases. The instruction

phase consists of the R/W bit, followed by the address of the

SDI input on the SCLK rising edges. The R/W bit specifies if the

SPI transaction is a register read or a register write. Set R/W to

1 for register reads and 0 for register writes. The AD4050/AD4056

also output a status word (STATUS_WORD) on SDO during the

instruction phase (see the Status Word section).

The addresses for all configuration registers are given in the Regis-

ter Summary section. The default length of the instruction phase

is 8 bits, with REG_ADDR length of 7 bits. The instruction phase

can optionally be extended to 16 bits, with REG_ADDR length of

15 bits, in order to clock out the entire STATUS_WORD. Set the

ADDR_LEN bit in the INTERFACE_CONFIG_B register to 0 to

extend the instruction phase to 16 bits.

Status Word

The AD4050/AD4056 instruction phase includes a status word

(STATUS_WORD) for transmitting basic device state information to

the digital host. The STATUS_WORD is clocked out on the SDO

pin during the instruction phase, as shown in Figure 62. Table 17

shows the contents of the STATUS_WORD. All STATUS_WORD

bits correspond to select bit fields from the configuration registers

(see the Register Details section).

The length of the STATUS_WORD is either 1 byte or 2 bytes long

and is equal to the length of the register access command as set

by the ADDR_LEN bit (see the Instruction Phase section). The

least significant byte of the STATUS_WORD is always included,

regardless of the ADDR_LEN setting. The most significant byte of

the STATUS_WORD is only included when the ADDR_LEN bit is

set to 0.

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