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AD4050BCPZ-R2 数据表(PDF) 38 Page - Analog Devices |
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AD4050BCPZ-R2 数据表(HTML) 38 Page - Analog Devices |
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38 / 67 page  Data Sheet AD4050/AD4056 MODES OF OPERATION analog.com Rev. A | 38 of 67 Autonomous Mode Diagrams Figure 60. Autonomous Mode Example Connection Diagram Figure 61. Trigger Mode Timing Diagram SLEEP MODE In sleep mode, the AD4050/AD4056 power down all functional blocks, except the digital interface, to achieve an ultra-low power consumption of 430 nW for extended periods of idle time (see Table 1). Set the POWER_MODE bit field in the DEVICE_CONFIG register to 2'h3 to put the AD4050/AD4056 into sleep mode. The internal LDO regulator is powered down and stops supplying the +1.8 V CLDO supply while in sleep mode. This feature powers down the ADC core and most other functional blocks. The digital interface remains active, so the digital host can rewrite the POW- ER_MODE bit field to 2'h0 to exit sleep mode and power up the device. When the device exits sleep mode, it enters configuration mode. The configuration register states persist, so the digital host does not need to reprogram the device configuration after exiting sleep mode. |
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