AD4050BCPZ-R2 datasheet(47/67 Pages) AD

47 / 67 page

Data Sheet

AD4050/AD4056

APPLICATIONS INFORMATION

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Rev. A | 47 of 67

Figure 71. AD4050/AD4056 Equivalent Input Load Model

Table 19. AD4050/AD4056 RC Kickback Filter Recommendations

Sample Rate

tACQ

RFILT

CFILT

−3 dB Bandwidth

2 MSPS

290 ns

100 Ω

1 nF

1.59 MHz

200 Ω

360 pF

2.21 MHz

1 MSPS

790 ns

250 Ω

1 nF

636.61 kHz

523 Ω

360 pF

845.30 kHz

500 kSPS

1790 ns

665 Ω

1 nF

239.33 kHz

1270 Ω

360 pF

348.10 kHz

100 kSPS

9790 ns

3.57 kΩ

1 nF

44.5 kHz

6.81 kΩ

360 pF

64.91kHz

Noise and Distortion Considerations

The noise and distortion specifications of the AFE circuit must

be considered, because they combine with the AD4050/AD4056

noise and distortion specifications to determine the overall system

performance. The total system noise (vN,TOTAL) is the root sum of

squares (RSS) of the AFE RMS noise (vN, AFE) and ADC RMS

noise (vN,ADC), referred to the inputs of the AD4050/AD4056 as

shown the following equation:

vN,TOTAL= vN,AFE2+vN,ADC2

(9)

MT-049 and MT-050 describe how to estimate vN,AFE for operational

amplifier circuits, as a function of the amplifier and passive compo-

nent noise specifications and amplifier configuration. The Front-End

Amplifier and RC Filter Design for a Precision SAR Analog-to-Dig-

ital Converter article describes how to estimate system SNR vs.

vN,AFE and vN,ADC.

As noted in the AD4050/AD4056 Equivalent Analog Input Model

section, the primary purpose of the RC kickback filter between

the AFE and the ADC is to minimize settling error and not to

filter AFE noise or perform anti-aliasing. The RC kickback filter

bandwidth cannot be set arbitrarily low, and it is recommended to

implement any additional noise or anti-alias filtering before or within

the amplifier circuit instead of the RC kickback filter. NP0/C0G type

dielectric capacitors are recommended for all capacitors used in

the AFE circuit to minimize signal distortion artifacts caused by

capacitor voltage and temperature derating.

REFERENCE CIRCUIT DESIGN

Equivalent REF Input Model

The AD4050/AD4056 require an external voltage reference to de-

fine the input range of the device. A low-noise, stable reference is

critical for maximizing accuracy and performance.

The AD4050/AD4056 REF pin draws charge (QCONV) from the

external reference circuit during each conversion phase to perform

the SAR ADC bit trials. The REF input current (IREF) can, therefore,

be expressed as a transient current load that occurs once per

conversion and as an equivalent average DC current load that is

a function of the sample rate (see Table 1 and Figure 18). The

voltage reference circuit must maintain a stable and accurate VREF

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