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AD4050BCPZ-R2 数据表(PDF) 59 Page - Analog Devices

部件名 AD4050BCPZ-R2
功能描述  Compact, Low Power, 12-Bit, 2 MSPS/500 kSPS Easy Drive SAR ADC
PDF  67 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD4050BCPZ-R2 数据表(HTML) 59 Page - Analog Devices

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Data Sheet
AD4050/AD4056
REGISTER DETAILS
analog.com
Rev. A | 59 of 67
Table 38. Bit Descriptions for ADC_MODES
Bits
Bit Name
Description
Reset
Access
7
DATA_FORMAT
ADC Output Format.
0x1
R/W
0: Straight Binary (Unsigned).
1: Twos Complement (Signed).
6
SIGN_EXT_EN
Sign Extension Enable Bit. Set this bit to enable the sign extension byte on ADC read data.
0x0
R/W
[5:4]
RESERVED
Reserved. Must be set to 0x0.
0x0
R/W
3
RESERVED
Reserved.
0x0
R
2
AUTO_MODE
Autonomous Mode Select Bit.
0x0
R/W
0: Monitor Mode.
1: Trigger Mode.
[1:0]
ADC_MODE
Operating Mode Select Bit.
0x0
R/W
0x0: Sample Mode.
0x1: Burst Averaging Mode.
0x2: Averaging Mode.
0x3: Autonomous Mode. Select between monitor and trigger modes via the AUTO_MODE bit.
ADC SETUP CONFIGURATION REGISTER
Address: 0x22, Reset: 0x00, Name: ADC_CONFIG
Table 39. Bit Descriptions for ADC_CONFIG
Bits
Bit Name
Description
Reset
Access
[7:6]
RESERVED
Reserved.
0x0
R
5
REF_SEL
Reference Source Select. Selects which pin is used as the ADC reference source.
0x0
R/W
0: REF.
1: VDD.
4
SCALE_EN
MON_VAL Scaling Enable. MON_VAL scaling is enabled when SCALE_EN is set to 1 while the input multiplexer
is configured to monitor the analog inputs (see the INP_MUX_SEL bit).
0x0
R/W
[3:2]
RESERVED
Reserved.
0x0
R
[1:0]
INP_MUX_SEL
Input Multiplexer Setting.
0x0
R/W
0x0: Analog Inputs. ADC connected to analog inputs (IN+ and IN−).
0x1: Invalid.
0x2: VDD/2. ADC monitors the VDD supply voltage scaled by ½ . This setting is used to determine the ratio of
REF to VDD and to set the MON_VAL scaling factor accordingly.
0x3: Invalid.
AVERAGING FILTER CONFIGURATION REGISTER
Address: 0x23, Reset: 0x00, Name: AVG_CONFIG



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