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FT600Q-FT601Q IC DatasheetDatasheet

Version 1.04

Document No.: FT_001118

Clearance No.: FTDI#424

The waveform below shows a FT601 master read transaction of 10 bytes with FIFO data exhausted first

at channel 1. There are turn-a-round cycles for DATA[7:0], DATA[31:16] and BE[3:0] after command

phase and at the end of the data transaction. The BE[3:0] shows that the lower 2 bytes in D2 are valid at

the last word strobe in this transaction.

In this waveform, there are 2 bus turn around cycles 1 and 2. The FIFO master releases the bus in bus

turns around 1, after which, the FT601 asserts the RXF_N indicating it drives valid data on the bus. The

FT601 releases the bus on bus turn around 2, the FIFO master should sample the FIFO status after the

bus turn around 2.

Figure 4.1 FT601 Multi-Channel FIFO mode master read transaction 1

The waveform below shows a FT601 master read transaction for 12 valid bytes at channel 1, where the

bus master terminates the transaction. There are turn-a-round cycles for DATA[7:0], DATA[31:16] and

BE[3:0] after the command phase and at the end of the data transaction.

* The data is valid when WR_N and RXF_N are both active.

Figure 4.2 FT601 Multi-Channel FIFO mode master read transaction 2

⃰In Multi-channel FIFO mode master read operation, the bus master shall be able to read out the

maximum possible data in the RX FIFO in one read transaction, i.e. when the FT600 or FT601 is

configured in the 1 channel Multi-channel FIFO mode, the bus master shall be able to read out 4 KB in

one bus transaction, and 2 KB or 1 KB in respect to the 2 channel or 4 channel mode. In write operation,

if the bus master expects the data to be transferred over USB bus in the maximum possible packet length, it

should write the data to the FIFO in a single bus transaction.

h’f

IDLE

Command

phase

Data output

Bus turn

around 1

around 2

Bus turn