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FT600Q-FT601Q IC DatasheetDatasheet

Version 1.04

Document No.: FT_001118

Clearance No.: FTDI#424

Please refer to the FT601 and FT600 application notes for alternate configurations:

http://www.ftdichip.com/Support/Documents/AppNotes/AN_370 FT600 Configuration Programmer User

Guide.pdf

E.g. Consider a USB 3.0 super-speed connection with a packet size is 1 KB, and a FIFO size of 4 KB.

Case #1: If the bus master completes a 4KB write in one transaction then this data will be transferred onto

the USB bus in 4 full sized packets.

Case #2: If the bus master completes a 1KB write in one transaction then this data will be transferred onto

the USB bus in a single packet (1 packet).

Case #3: If the bus master completes a 1025 byte write in one transaction then this data will be transferred

onto the USB bus in one full sized packet with length of 1024 bytes (1KB) + one short sized packet with a

length of 1 byte.

The waveform below shows a FT601 master write transaction for 14 bytes at channel 1 with the bus

master terminating the transaction. There are turn-a-round cycles for DATA[15:8] after the command

phase and at the end of the data transaction. The BE[3:0] shows that the lower 2 bytes in D3 are valid at

the last word strobe in this transaction.

Figure 4.3 FT601 Multi-Channel FIFO mode master write transaction 1

NOTE: There is no turnaround phase for BE pins as these remain inputs when the FIFO is being written to

by the master.

The waveform below shows a FT601 master write transaction where the FIFO at channel 1 uses all data

space first, the RXF_N reasserts when the FIFO data space is not available after D3. There are turn-a-

round cycles for DATA[15:8] after the command phase and at the end of the data transaction. The

BE[3:0] shows that the transaction is all in word aligned, all 4 bytes in D3 are valid at the last word

strobe in this transaction.