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16

FT600Q-FT601Q IC DatasheetDatasheet

Version 1.04

Document No.: FT_001118

Clearance No.: FTDI#424

Figure 4.4 Multi-Channel FIFO mode master write transaction 2

The waveform below shows a master read of channel 1 followed by a master write to channel 1.

The channel number is selected in the command phase (DATA[7:0] = h’01 for channel 1 in this case),

and data is transferred on the same data pins multiplexed to a different channel.

Figure 4.5 Multi-Channel FIFO mode master read followed by write transaction

4.3

245 Synchronous FIFO mode Protocols

This FT601 and FT600 slave FIFO bus uses one IN and one OUT FIFO channel while in this mode.

CLK is the clock output to the bus master; it can be configured as 66 MHz or 100 MHz

TXE_N is an output signal, Transmit FIFO Empty. It is active low and when active it indicates the

Transmit FIFO has space and it is ready to receive data from the FIFO master.

RXF_N is an output signal, Receive FIFO Full. It is active low and when active it indicates the Receive

FIFO has data and it is ready to be read by the FIFO master.

OE_N is an input signal, Output Enable. It is active low and when it is driven low by the bus master, the

slave will drive the data and byte enable buses.

WR_N is an input signal, Write Enable. It is active low and when it is driven low by the bus master, the

master has write cycle access.

RD_N is an input signal, Read Enable. It is active low and when it is driven low by the bus master, the

master has read cycle access.